#asahi-re on 2022-04-04 — irc logs at oftc.irclog.whitequark.org

2022-03-22 11:58 ChanServ changed the topic of #asahi-re to: Asahi Linux: porting Linux to Apple Silicon macs | Hardware / boot process / firmware interface reverse engineering | WARNING: this channel (only) may contain binary reverse engineering discussion | RE policy: https://alx.sh/re (MANDATORY READ) | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-re

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12:35 <YichaoYu[m]> I noticed that a failed cas instruction seems to be about 2-10x slower than successful ones, depending on the memory order on the m1. And I don't see this on intel.

12:36 <YichaoYu[m]> it also generates many more counts on the counters that I suspect related to uops issued.

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12:37 <YichaoYu[m]> I don't really know how people implement atomics these days but is it possible that these atomic operations are actually ucoded and internally it's still using something similar to llsc?

12:38 <YichaoYu[m]> and this difference is especially pronouced with more relaxed ordering, and especially on the P cores

12:40 <TellowKrinkle[m]> I remember seeing on the Swift forums that Apple CPUs have no performance penalty for uncontested atomic refcounting (which Swift used CAS for), so they definitely optimized the success case

12:40 <TellowKrinkle[m]> Whether that was to the detriment of the failure case I don't know

12:41 <YichaoYu[m]> note that I'm talking about single thread here

12:41 <YichaoYu[m]> I was basically doing a cas with the wrong compare value with no contention.

12:42 <_jannau_> do you target armv8-a. or armv8.1-a (or later)

12:42 <YichaoYu[m]> and yes, successful weak ordering cas is really cheap

12:43 <YichaoYu[m]> yes when I cross-checked it in julia, and for my original test it's hand written assembly

12:43 <YichaoYu[m]> asm here https://github.com/yuyichao/m1_pmu_test/blob/cf4fbcc3e740e258339637c64062385a140c666b/src/libtests_atomic.s#L241-L246

12:43 <_jannau_> the first will give you load/store exclusive atomics the later has explicit atomic instructions

12:44 <YichaoYu[m]> and the fail case ~20 lines below

12:44 <YichaoYu[m]> (hand writen -> script generated...)

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12:47 <YichaoYu[m]> for a successful relaxed ordered cas with no contention, the loop takes 3 cycles on the P core (compared to ~1 cycle if it was a simple store).

12:47 <YichaoYu[m]> if the comparison failed, still with no contention, it takes 58 cycles per loop on the p core

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12:51 <YichaoYu[m]> on a related note, a failed cas does generate a count on the counter where a failed stxr does (180/0xb4)

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