16:37 <calebccff> bryanodonoghue: lumag: so i took another look at the op6 camera stuff, ran debugcc and it turns out the mclk is running at 6MHz instead of the 24MHz it should be at

16:37 <calebccff> this would likely explain the lack of data on the CSIPHY

16:58 <calebccff> also since i rebased on 6.9 I'm getting "rcg didn't update its configuration" messages for the ife_0_clk_src clock

16:58 <calebccff> removing all except the first vfe/csid/csiphy in the resource tables seemed to fix it?

17:38 <calebccff> huh

17:38 <calebccff> so most of the clock rates are just totally wrong

19:48 <bryanodonoghue> calebccff unless you are in the middle of capturing all of the clocks will be at their lowest value

19:49 <bryanodonoghue> start a capture - ctrl+z - then cat /sys/kernel/debug/clk/clk_summary | grep camcc

19:50 <bryanodonoghue> also make sure you have the *right* csiphy_timer clock

19:50 <bryanodonoghue> one is for the PHY state machine

19:50 <bryanodonoghue> the other is for recovering bits on the wire

19:51 <bryanodonoghue> Unfortunately ATM the order of clock declaration in camss/dtsi matters

19:51 <bryanodonoghue> Another fix that needs to be implemented

19:53 <bryanodonoghue> you should see something like csiphy0_timer @ 300MHz

19:54 <bryanodonoghue> lots of the default parameters in the magic phy sequence are predicated on that clock running at that rate

19:54 <bryanodonoghue> mclk @ 6Mhz isn't necessarily wrong its an input to the sensor

19:55 <bryanodonoghue> its up to the sensor to clock the CSIPHY

19:56 <bryanodonoghue> something like 24MHz would be a bit more normal though