01:12 <TortillaRetreat> Alright, what are the immediate to-dos as far as the code is going?

01:44 <chadmed> i believe focus rn is on mapping the rest of the chip and figuring out how to control it

08:06 <arnd> kettenis: IIRC "dma-coherent" should be a property of each bus node that is a parent of a dma-capable device, same as "dma-ranges"

08:07 <arnd> so if there are hierarchical buses, put the properties in both the parent and child buses

08:20 <kettenis> arnd: hmm, the device tree specification talks about devices instead of busses

08:20 <arnd> ok, I'm probably misremembering it then

08:21 <arnd> dma-ranges should definitely be in all the bus nodes, it seems we went the other way with dma-coherent for some reason

08:22 <kettenis> I think I've seen SoCs with both coherent and incoherent devices on the same bus

08:24 <kettenis> but this seems to argue for dma-coherent properties on the usb, nvme and pcie "devices" instead of putting a single one on the /soc simple-bus node

08:30 <arnd> Right. The idea of what a "bus" is in DT doesn't really match the reality of modern SoCs any more, where you have lots of point-to-point links that can have different behavior. It used to be that dma-ranges and coherency were fundamentally tied to the physical bus implementation