01:10 <shawnguo> aka_[m], yeah, I am

02:29 <bamse> rawoul: and you had a problem with an MDSS clock, which would imply that some parent isn't ticking properly...and if that parent is part of MDSS, it probably need MDSS_GDSC to be on, to be powered

02:30 <bamse> Mis012[m]: if, like many other platforms, MDSS_GDSC is powered by VDDCX, then that should be modelled such that MDSS_GDSC is a subdomain of the VDDCX power-domain, doing that will result in requests on the GDSC propagating up to the VDDCX as necessary

02:31 <bamse> Mis012[m]: but that's a rather recent thing we've been working on, so that's not going to be in place for 8998

03:47 <aka_[m]> shawnguo: I seen you were working on 8939 stuff, from what i see cci also uses 200mhz as safe clock, do you have any patch to set custom divider inside apcs-msm8916.c?

03:47 <aka_[m]> Rn it sets static 4

03:50 <shawnguo> aka_[m], I would point you to bryanodonoghue who is still working on 8939 recently

03:52 <aka_[m]> Ok, thanks.

05:17 <bryanodonoghue> aka_[m] Jun Nie and Leo Yan have done a whole bunch of CPR enabling work - including some CPR fuse settings for the CCI on 4.19 which we are actively working to release asap

05:18 <bryanodonoghue> I did a very quick pass at forward porting it to 5.x to release upstream but it didn't "just work" straight away so I dropped it

05:19 <bryanodonoghue> so we do have cpr code for the cci bus which testing in the wild has shown to be important to have

05:19 <bryanodonoghue> hope to publish something really relatively soon on 4.19

05:20 <bryanodonoghue> CPR feels like a big enough topic to separate out from the inital 8939 dtsi though

06:23 <aka_[m]> Nice.

06:23 <aka_[m]> Tho cpr is hard to understand if you don't know how it works.

06:23 <aka_[m]> I had quite a lot of issues understanding 8976 dts part for it.

15:13 <aka_[m]> Do any of you qcom folks can say what is main difference between HF pll and HF2 one?

15:13 <aka_[m]> HF one is used on qcs404

17:46 <minecrell> aka_[m]: I don't think you should care about 200 vs 400mhz safe frequency unless it really noticeably breaks something. This might be just a random choice

17:46 <minecrell> The main important thing is that the CPU is temporarily switched from the PLL while it's being reconfigured

17:46 <minecrell> The frequency you use for that probably doesn't matter too much imho

18:05 <aka_[m]> well when it switches it to gpll0 it also set divider for this gpll0 source

18:05 <aka_[m]> maybe its about doing it on low enought freq so we won't break something if our CX is like low_svs or something

18:14 <minecrell> aka_[m]: the PLL provides the higher frequencies, so if you're reconfiguring it because you want to switch from $high-freq to $some-other-high-freq then CX should be already voted for $high-freq. And this should be more than sufficient for the $low-freqs of GPLL

18:14 <minecrell> just imho again though

18:41 <abhinav__> rawoul great to see the dpu support on 8998 and your WIP tree. Looking fwd to reviewing that on the list.

18:41 <abhinav__> not an expert on the power domains either

18:41 <abhinav__> but if that has been ruled out

18:41 <abhinav__> as the issue

18:41 <abhinav__> my next clue to you would be to look into the PLL driver

18:41 <abhinav__> for the rate you are setting