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<minecrell> aka_[m]: yes, I believe the secure gpu context bank exists on 8916 as well. But I kinda doubt it's used for anything on mainline, sounds more like a DRM thing
<z3ntu1> lumag: uh what do you mean with "generic driver"? You mean like qcom,smmu-v2 for gpu?
<aka_[m]> uh
<aka_[m]> he meant if qcom,msm-iommu-v2 works fine then you can use it
<aka_[m]> wrong
<aka_[m]> eh
<aka_[m]> lumag: it might work as long as you don't define secure bank
<aka_[m]> once you do v1-sec might crash because i believe v2-sec do something bit different
<aka_[m]> there is also thing about TZ calls and context bank!=asid parameter
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<z3ntu1> aka_: but using -v1-sec on 8953 appears to work, but I'm guessing just because it's not actually using the secure context bank?
<aka_[m]> z3ntu1: v1 on gpu?
<aka_[m]> you can check if this context bank work with v1-sec
<aka_[m]> on 8976 when i defined it long time ago with v1 sec i had panic
<z3ntu1> aka_: yes I tried that a few days ago, at least probe and basic smoke test of gpu worked fine. But as I said, I guess currently gpu doesn't use the @2000 context bank so maybe that's why nothing breaks
<lumag> z3ntu1, it's a5xx, so the usage should be pretty simple. My questions was if you can use arm-smmu driver for adreno_smmu.
<lumag> BTW, I know that at some point there was a patch to enable per-process pgtables for a5xx, https://lore.kernel.org/linux-arm-msm/1559163292-4792-17-git-send-email-jcrouse@codeaurora.org/ . robclark, do you remember why was it dropped?
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<z3ntu1> lumag: okay, will check and let you know
<lumag> z3ntu1, I mean, I have considered msm-iommu driver to be a workaround for the TZ issues present on some of the platforms. If possible, we should be using the arm-smmu driver.
<lumag> z3ntu1, btw#2: could you please check if the endpoint issue was related to https://lore.kernel.org/linux-arm-msm/ZXqr0RFw9KsP876v@hovoldconsulting.com/ ? I don't remember i I asked you about the qrtr being =y or =m
<aka_[m]> lumag: some old code sits there
<lumag> aka_[m], oh, wow. Maybe z3ntu1 can make use of that
<bryanodonoghue> calebccff how is 2 lane mode going for you ?
<aka_[m]> but you need to upstream that impl
<aka_[m]> and @vladly for some reason decided to abandon that and use qcom,iommu
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<z3ntu1> I've no clue what's a better approach with iommu tbh, I'd be happy just using msm-iommu driver since it appears to work fine etc
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<calebccff> bryanodonoghue: no dice, spoke to kbingham and I'm reaching out to the developer @ IoB who's been working on it - apparently they have the sensor working with the generic CCS driver
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<robclark> lumag: I think that by the time we'd come up with a solution for the arm-smmu side of things that was acceptable to the iommu maintainers, we were working on a6xx.. so probably no good reason not to resurrect the a5xx bits (the interface to arm-smmu side of things is somewhat different but the a5xx code can just re-use what is already there). It should be restricted to devices w/ apriv but I think preemption is also
<robclark> restricted to things w/ apriv
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