14:58 <calebccff> bryanodonoghue: thanks. I was checking the clocks with sdm845-debugcc -b cam -a while capturing (or attempting to, clocks were all on though). The thing is the rates reported by debugcc don't match at all what's in debugfs

15:00 <calebccff> bryanodonoghue: after messing with the camcc-sdm845 driver a bit there seems to be an extra divide by 4 somewhere, I was able to get the mclk frequency to match by fiddling with the RCG but the timer clock is still 1/4 of what it should be https://p.calebs.dev/9df8d4@raw

15:00 <calebccff> note that debugfs reports the correct rates for it

15:01 <calebccff> it should be 270MHz but it's actually 67MHz

15:02 <calebccff> the RCGs have the CLK_SET_PARENT_RATE flag, where the parent is the PLL

15:02 <calebccff> the PLL postdiv even*

15:02 <calebccff> but the set_rate cb is never called for the postdiv or the PLL itself

15:03 <calebccff> there's a weird comment about that flag being needed specifically for PLL2_OUT_EVEN (which is what mclk0 is derived from) but it's all just odd

15:03 <calebccff> hoping lumag has some ideas

15:07 <calebccff> unless the div4 is a bug in debugcc /shrug

15:52 <aka_[m]> calebccff: i wonder

15:52 <aka_[m]> how this clock can achieve such rate

15:54 <aka_[m]> your problem is with cam_cc_csi0phytimer_clk_src ?

16:07 <aka_[m]> ok thats too complicated for my taste

16:07 <aka_[m]> and i still wonder why clk code is so confusing

16:07 <aka_[m]> there is EVEN but there is no enable reg and no enable mask

16:08 <aka_[m]> i know it could be enabled by "reset value"

16:09 <aka_[m]> but why don't we have .enable ops do something like .is_enabled and then if things match just not do pll->is_enabled = true or whatever