<gch981213>
jeff___m: Does the affected module come from kernel or backport? You might try patching the in-kernel version instead of backport.
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<jeff___m>
@gch981213: how do I tell where the module is coming from? Probably in kernel, its /include/linux/mhi.h and /drivers/bus/mhi/host/boot.c
<jeff___m>
That's a good point I just assumed since those files existed in the backports package it was getting headers from there, I shall patch them in the kernel as well and try that.
<gch981213>
jeff___m: A quick check is to see if the used kmod- package is defined in package/kernel/mac80211. If it's not, the module used is from the kernel.
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<rmilecki>
Ansuel: in my case PHY driver uploads 124384 B (0x1E5E0) and 247104 B (0x3C540)
<rmilecki>
Rhe-05.06-Candidate9-AQR_Mediatek_23B_P5_ID45824_LCLVER1.cld is 393218 B (0x60002)
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<Ansuel>
robimarko i can totally say the -110 problem is a real PITA
<robimarko>
I can agree on that
<Ansuel>
rmilecki just to confirm you also suffer from the timeout error with the aquantia phy or yours works correctly?
<rmilecki>
Ansuel: my board has 2 x AQR113C
<rmilecki>
first one gets initialized fine
<rmilecki>
second one suffers from race and I get -110
<robimarko>
I have exactly the same issue with 2xAQR113C
<rmilecki>
i've two working workarounds: 1. wait for completion patch 2. speed up MDIO bus
<robimarko>
But even weirder, in my case it doesnt even probe the second one
<robimarko>
for a long time
<Ansuel>
so at least the first PHY load the firmware correctly and works?
<Ansuel>
(from a correctly flashed image not initramfs)
<robimarko>
It loads the FW, but then later it fails as well
<rmilecki>
Ansuel: without any changes, yes, first PHY works well with upstream code
<rmilecki>
oh, in my case firsr PHY seems fine
<Ansuel>
we are missing some funny settings so i wonder if keeping the default values cause problem on the other aqr PHY
<Ansuel>
there is one settings for MDIO broadcast that is set to 1f by default and should be changed to the PHY address (this is what is done in the firmware load)
<Ansuel>
(original code)
<Ansuel>
(upstream doesn't have this)
<robimarko>
Is MDIO broadcast even enabled by default in the PHY
<robimarko>
That should be disabled for sure
<robimarko>
Any sane PHY doesnt enable it by default
<robimarko>
Bit 14 in Global General Provisioning 2 enables/disables that
<Ansuel>
they enable that
<robimarko>
But datasheet says its disabled by default
<robimarko>
I guess they are using it to load the FW on multiple PHY-s at once
<Ansuel>
also after the load they sed bit 4 to 1
<Ansuel>
open drain mode
<robimarko>
Yeah, that is MDIO drive configuration
<robimarko>
Now, it would be awesome to print that register MMD 1E, 0xC441 after U-Boot does network init
<robimarko>
As then it magically works
<Ansuel>
thing is that on nbg the thing doesn't even work o.O
<Ansuel>
i tried to apply the same exact regs the uboot implementation does
<Ansuel>
the damn thing doesn't accept the fw...
<Ansuel>
(dumping the FW_ID always returns 0)
<robimarko>
Reset has been disabled?
<Ansuel>
you mean remove the entry in dts?
<robimarko>
No, I mean has the reset GPIO been disabled?
<robimarko>
AKA PHY put out of reset?
<Ansuel>
yes i also made some experiment with that
<robimarko>
Though you wouldnt even be able to communicate if it wasnt
<Ansuel>
if it's in reset those regs returns 0xffff
<robimarko>
Yeah
<robimarko>
I used mdio tool to verify the reset pin
<Ansuel>
we are also missing the 100ms delay for reset to complete from documentation but that is unrelated it seems
<robimarko>
Then you can manually trigger it and see if it dissapears
<robimarko>
100ms?
<robimarko>
That is way too much
<Ansuel>
page 119
<Ansuel>
3.3 Reset
<robimarko>
Where the hell did you get page 119?
<robimarko>
AQR113 datasheet is only 93 pages
<Ansuel>
i have a random vertical datasheet for aqr405 that is 688 page
<robimarko>
AQR405 is a completey different generation
<robimarko>
I guess they include registers as well in that
<Ansuel>
everything matched currently
<robimarko>
But yes, 100ms is the full reset time
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<Ansuel>
starting to think there is something bad in the mdio configuration...
<robimarko>
Hopefully I wrap up this U-Boot DHCP nightmare at work and can poke around again
<robimarko>
Have you tried flashing the image
<robimarko>
Then interrupting U-Boot and booting the flashed image from it?
<robimarko>
That made it work for me
<Ansuel>
btw with the delay even from initramfs you can trigger the fw load
<Ansuel>
and with that it does work
<Ansuel>
i guess this is something you did't try?
<Ansuel>
(gpio reset should cause the firmware to be wiped correct?)
<robimarko>
Hm, I guess it should
<robimarko>
So, its rather a good question why it doesnt
<robimarko>
I can only guess that the reset pulse is too short
<Ansuel>
cause we didn't had the delay
<Ansuel>
i notice this while checking what was done on gpio 63
<Ansuel>
adding a debug print was enough to introduce enough delay for the PHY to correctly reset
<Ansuel>
(in initramfs load)
<robimarko>
Yeah, I only tried adding assert and deassert delays for the flashed image
<Ansuel>
so my theory is that there is nothing wrong in the phy itself
<Ansuel>
but something somewhere else... and not even gpio
<Ansuel>
or maybe the gpio config?
<robimarko>
I can only guess that the reset length is too short
<Ansuel>
what they do in uboot is
<robimarko>
And that assert delay doesnt really change the pulse length