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<
nickchan >
currently dealing with some cache issues on A7 that might be a Cyclone erratum...
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<
nickchan >
a lot of corellium-isms turns out to be required... on these old cores
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<
nickchan >
okay yeah it's an erratum
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<
nickchan >
that needs runtime tunable flipping
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<
nickchan >
not just at init
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<
nickchan >
> Cyclone UM 5.3.8.3
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<
nickchan >
I
*don't* think this needs a workaround in linux yet
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<
nickchan >
in summary: dc cvac does nothing and dc civac does nothing unless a bit in a register is flipped
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<
nickchan >
marcan: so... why is HID4_DISABLE_DC_MVA set by default anyways
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<
nickchan >
on all cores
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<
maz >
nickchan: could be related to the fact that recent SoCs don't actually need CMOs to the PoC as all devices are cache coherent.
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<
maz >
may also snoop non-cacheable accesses.
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<
nickchan >
maz: these bits are set by xnu on every core as well even on a7
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<
nickchan >
so it is more likely that something is going to be broken without the bit set
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<
nickchan >
But cache maintenance on a7 needs the bit unset it
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<
nickchan >
so what I see is XNU set the bit to avoid problems but when doing cache maintanence unset it, do the instructions, then set it again
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<
maz >
nickchan: my comment was about M1+ CPUs, indicating why CMOs don't need to do much.
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