ChanServ changed the topic of #asahi-dev to: Asahi Linux: porting Linux to Apple Silicon macs | Non-development talk: #asahi | General development | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-dev
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<nickchan>
anyways about the typec i will surely say that using checkra1n over and over is a great way to make the ports explode and dead until next reboot
<nickchan>
okay it's not as bad as I made it out to be but it happens sometimes more than the background noise
<sven>
you mean running checkra1n on a asahi linux machine?
<sven>
not surprising then tbh, doesn't it trigger a reset in the middle of a transaction?
<nickchan>
sven: right every checkm8 tool needs to do that
<nickchan>
but yeah I use it because the m1 pro is the fastest machine i can compile linux on and then boot it on an iphone
<nickchan>
(right now it's the only machine I can sanely do that even)
<sven>
yeah, and resets are already a bit sketchy with the current dwc3/atcphy driver
<sven>
so not very surprising the ports gets into a weird state eventually
<sven>
we won't merge any m3 support into our kernel trees for now
<sven>
how have you confirmed that you changes w.r.t. that pmu thing are correct?
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<fl0_id>
sven yeah that's what I thought
<sven>
we're rebasing on upstream each release though so if you want m3 device tree in our kernel better send them to LKML ;)
<fl0_id>
sven I have "confirmed" it in so far that with that, the dumping and other things work in m1n1. But I don't know enough to say if that introduces some weird errors or similar, that's why I am asking. If I remember correctly, mischa85 who did some m4 work also had to do a similar fix.
<fl0_id>
sven for now I would just be happy to play around with it haha
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<sven>
what if you just skip writing to that reset counter? does that change any behavior?
<sven>
ideally i'd like to understand what actually changed before merging that
<sven>
and nothing's stopping you from playing around with m3, just add the device tree locally
<sven>
and if that change is confirmed like that probably just gate it on the pmu compatible instead of isinstance(..., int) if possible
<fl0_id>
sven i haven't tried that yet but could maybe do that this week. right now I am just kind of sick and trying to distract myself haha
<fl0_id>
yeah understanding would be good
<fl0_id>
ok thx for the pointers. I would have to get a diff device tree then the one linked above anyway, as I only have the m3 max
<sven>
that device tree already does way too much tbh :D
<sven>
initially you should only need aic and uart plus dependencies I think
<sven>
also skip all the pmgr nodes
<sven>
oh, and framebuffer maybe if you want penguins
<nickchan>
Don't really need pinctrl for bringup I think but wdt can be good
<sven>
i'd also drop pinctrl there
<sven>
yeah
<sven>
agreed
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<nickchan>
speaking of 8015 ans2 fw already successfully booted now dealing with some command_id/tag weirdness, and there's no nvmmu or linear sq
<nickchan>
(in linux)
<nickchan>
after that i will fix some tech debt like usb not having phy and using bootloader state for bus configuration and such
<nickchan>
which will also make it upstreamable
<sven>
ugh, that's gonna require some invasive changes to nvme/apple.c then
<sven>
how does command submission work then? more similar to regular nvme?
<nickchan>
it's nvme but less bastardized than m1
<sven>
might make sense to create apple-iphone.c or something like that then
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<nickchan>
working now:)
<nickchan>
mailbox - i2a and a2i control has different offsets that's about it; sart is sartv0 and uses a different set of allow flags and 36 bit pa
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<sven>
v0? huh
<sven>
i think M1 was already v2
<nickchan>
a14 is v1 appearently
<sven>
ah well, don't think we'll ever support that one
<nickchan>
sart is something that could be figured out just by reading out what iboot configured the register as and then try writing 0xffffffff to it
<nickchan>
and see which bits can be set
<nickchan>
currently calling the mailboxes "apple,t8015-marin-mailbox", "apple,marin-mailbox" since the mbox for the kingfisher cores is most definitely different
<nickchan>
erm I mean mailboxes for the cortex-a7 cores
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<fl0_id>
sven ok
<fl0_id>
sven thx. let's take it one step at a time ;)
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<sven>
would be nice if someone could test https://github.com/AsahiLinux/m1n1/pull/447 on linux. seems to work fine on macos and with that i can finally get rid of my local patches that i keep stashing/unstashing to make proxyclient work here :D
<nickchan>
sven: and a7-a11 cores definitely has more rev specific chickens it is just quite unlikely the chickens for previous revs will ever be used
<nickchan>
at least no one should run m1n1 on Alcatraz (A7) A0
<nickchan>
and that horrdenously *broken* given that it's an arm64 core fabbed in 2012
<sven>
sure, i just wanted to get rid of all these if (part >= WHATEVER && part != SOMETHING_ELSE)
<sven>
especially because with M4 we'd need && part <= T8132_DONAN all over the place
<sven>
*<
<nickchan>
think it's a good idea to open code everything too since there's always some Apple Watch cores or ASC cores in the middle breaking the flfow
<nickchan>
which this refractor als odo
<nickchan>
also do
<nickchan>
talking about midr comparisons
<sven>
yeah, and also makes adding new things less scary because it's obvious to see what's going on
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<nickchan>
sven: i do think the CYC_OVRD_DISABLE_WFI_RET bit should be cleared on startup on cores that supports arch state retention
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