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<alyssa>
lina: We need a plan for getting MSAA reviewed+merged
<alyssa>
Maybe we want to schedule a code walkthrough stream so we can do review synchronously and I can fix any issues as they're pointed out in real time?
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<alyssa>
Ditto for live range splitting in the register allocator.
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<ChaosPrincess>
sorry for dumb questions, but do all gpu compilers have their own bespoke register allocators?
<alyssa>
ChaosPrincess: In mesa, yes
<alyssa>
No idea about LLVM, since only AMD upstreams their LLVM compiler
<alyssa>
(Intel has a source dump somewhere but I have enough self respect not to look at it)
<alyssa>
not a dumb question at all
<alyssa>
We've waffled about trying to share RAs in Mesa but... different GPU ISAs are radically different in their RA requirements that it's not clear if that can be done efficiently
<ChaosPrincess>
well, read dumb = "my only interaction with gpus is 'i wrote an opengl renderer for some chemistry stuff in school' and i havent touched them since"
<alyssa>
we do have a common graph colouring engine (util/ra), which ~~dinky~~ other compilers us
<alyssa>
use
<ChaosPrincess>
and iirc llvm shares parts of their register allocators
<alyssa>
the valve compilers are all SSA-based RA
<alyssa>
which is really great for generated code quality + low compile-time
<alyssa>
and very not great for huge complexity and specificity to the ISA in question
<alyssa>
it's not clear what, if any, code could be shared between the SSA RAs
<alyssa>
probably almost nothing if we're using C
<alyssa>
if we were all writing c++ or rust compilers it *might* be different but I'm not convinced
<ChaosPrincess>
eh, i wouldnt throw out random unresearched suggestions :P
<alyssa>
>:)
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