#asahi-re on 2021-01-25 — irc logs at oftc.irclog.whitequark.org

2021-01-11 09:52 marcan changed the topic of #asahi-re to: Asahi Linux: porting Linux to Apple Silicon macs | Hardware / boot process / firmware interface reverse engineering | WARNING: this channel (only) may contain binary reverse engineering discussion | RE policy: https://alx.sh/re (MANDATORY READ) | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-re

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18:32 <bastilian> The keyboard clickity-clack from the streams is my ASMR

18:36 <davidrysk[m]> marcan: are you sure that migration is unused on the m1?

18:36 <davidrysk[m]> I'd expect it to be useful if the scheduler decides that a process does not need to be on a p-core anymore

18:36 <davidrysk[m]> (does linux support migration for regular ARM BIG.little and if so how?)

18:38 <davidrysk[m]> yeah there's https://www.kernel.org/doc/html/latest/scheduler/sched-energy.html

18:41 <marcan> davidrysk[m]: but the cores run in parallel

18:41 <marcan> the scheduler can just do it

18:41 <marcan> there is no need for hardware assistance

18:41 <marcan> the migration stuff is necessary for the socs with mutually-exclusive cores

18:42 <marcan> linux can just randomly decide to schedule a process on a different core at any time

18:42 <marcan> for M1 type stuff with both clusters on at once

18:43 <davidrysk[m]> so there's no need to mess around with ARM64_REG_MIGSTS_EL1?

18:44 <davidrysk[m]> heh they're only using that to dump error state anyway

18:51 <j`ey> davidrysk[m]: what migration were you referencing?

18:51 <davidrysk[m]> p-core to e-core

18:51 <davidrysk[m]> and vice versa

18:51 <j`ey> right, but I was confused by your initial "are you sure that migration is unused on the m1?"

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18:51 <j`ey> was that referenecing something marcan said?

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18:58 <marcan> on stream I said we didn't need any of that migration stuff on this chip

18:58 <davidrysk[m]> I'm referring to MIGSTS and related registers

18:58 <davidrysk[m]> though it appears that Apple only uses the MIGSTS register when dumping error state

18:58 <marcan> that register does not even exist any more

18:58 <marcan> #define SYS_APCTL_EL1 sys_reg(3, 4, 15, 0, 4)

18:58 <marcan> it became that

18:59 <marcan> same encoding

18:59 <davidrysk[m]> hah

18:59 <marcan> corellium messed that up in their chickenbits dump and documented it as MIGSTS or whatever

18:59 <davidrysk[m]> they... reassigned it as a register used for PAC

18:59 <marcan> yes

18:59 <j`ey> marcan: hm, did you make up the name SYS_APCTL_EL1 then?

19:00 <davidrysk[m]> which means the newer CPUs don't have HAS_MIGSTS

19:00 <davidrysk[m]> j`ey: SYS_ -- apple calls them ARM64_REG_blah

19:00 <j`ey> ah right

19:03 <davidrysk[m]> Apple's PAC implementation has separate keys for kernel and user mode and is quite a bit more robust

19:03 <davidrysk[m]> but I doubt upstream would take an Apple-specific implementation like that

19:07 <j`ey> maybe if other CPUs implement it too

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