ChanServ changed the topic of #asahi-re to: Asahi Linux: porting Linux to Apple Silicon macs | Hardware / boot process / firmware interface reverse engineering | WARNING: this channel (only) may contain binary reverse engineering discussion | RE policy: https://alx.sh/re (MANDATORY READ) | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-re
<marcan>
amarioguy: it being a priority thing tracks (what I don't know is how you set IRQ priority then, though)
<marcan>
and yes, no expectation that this would affect FIQs
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<amarioguy>
marcan: in other words it's time for scientific method testing :) (i'd realistically only need to test this on 2-4 cores or so and store the data on how many IRQs each core gets at what settings)
<marcan>
I mean, I imagined there's some setting for each individual IRQ that sets priority, and thus which subsets of cores can get it
<marcan>
but I might be wrong
<marcan>
I don't remember seeing anything like that in AIC2
<amarioguy>
fwiw the register only supports setting bit 0 and bit 1 so i doubt you're gonna get much with only two bits
<amarioguy>
it affects the heuristic that much is for sure
<amarioguy>
probably can gather a lot of the runtime data for values of 0x1 and 0x2 this weekend
<amarioguy>
but it may just be like that CYC_OVRD reg where 0 is on, 2 is off and 1 is.... just unused to my knowledge
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<marcan>
amarioguy: you'de get 4 priority levels with 2 bits, which is useful
<marcan>
*you'd
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