03:40 <marcan> q3k2: I looked at that (mostly blind over the same UART lol), IIRC the closest relative was S3C2400 but some things were moved around

03:41 <marcan> did you look at the bit defines from linux?

03:43 <marcan> also IIRC these chips only have edge triggered IRQs, so you need to get the sequencing right

03:43 <marcan> i.e. RXTO won't fire if you enable it with stuff already in the FIFO

03:44 <marcan> internally edge triggered that is

03:44 <marcan> you need to make sure the IRQs are enabled (possibly masked at the IRQ controller, but enabled as far as the UART goes), clear the UTRSTAT bits (they're write 1 to clear), drain the RX FIFO, and then you should get an IRQ next time a byte comes in and times out

10:06 <q3k> marcan: yeah, i think i have all of this correct. i am getting the rx threshold interrupt, just not the timeout interrupt. pretty sure sequencing is also correct, i'm 'just' using the linux driver already there, and even if it's broken at startup then during the next threshold-driven drain of the fifo things should re-sequence correctly.

10:07 <q3k> the only thing i've found so far is that if i poke some other bits in UTCON i start getting interrupts on another IRQ, but that still doesn't seem to be the rx timeout.

10:07 <q3k> i guess i'll just continue poking at it and re-re-read the original firmware's implementation

10:08 <q3k> s,UTCON,UCON,

10:13 <marcan> q3k: I believe the original implementation had discrete IRQs, then Apple merged them into one, so it's possible that one still has them split

10:13 <marcan> might want to compare with S3C2400 which has the RX TO enable bit in a different position

13:10 <ChaosPrincess> q3k: you might want to look at what sandcastle people are doing. though caveat emptor on their code, i recommend checking it before using