ChanServ changed the topic of #asahi-re to: Asahi Linux: porting Linux to Apple Silicon macs | Hardware / boot process / firmware interface reverse engineering | WARNING: this channel (only) may contain binary reverse engineering discussion | RE policy: https://alx.sh/re (MANDATORY READ) | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-re
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<nickchan>
chaos_princess: for voltages and frequencies, on m1 have you experimented with the registers at cluster->base (in m1n1 cpufreq.c terms) + 0x70000 ?
<nickchan>
this supposedly holds definitions for each pstate in strides of 0x20, for state 0-15 on m1
<chadmed>
do you think writing to them will change the regulator behaviour at each pstate?
<nickchan>
chadmed: it very much does on a7-a11, t2 (different offset and different stride size on some chips)
<nickchan>
a simple experiment is to try to, say, overwrite definition of state 3 with definition of state 4
<nickchan>
and see if the experiments/cpu_pstate_latencies.py has anything to say about it
<chadmed>
but how do we confirm that its _actually_ changing what the regulators are doing
<chadmed>
scratch up some tracks? :p
<nickchan>
I cranked up A9 to 2448 MHz and A11 to 2112 MHz Ecore 2376 MHz Pcore like that
<nickchan>
with the cpu_pstate_latencies experiments
<nickchan>
it measures the frequency
<chadmed>
cool but we know we can change the frequency. we want to know if the voltage _actually_ changes
<chadmed>
i guess we could just overwrite pstate 0 with the definition for the highest turbo pstate and see if it doesnt crash
<nickchan>
yeah that
<nickchan>
well state 0 doesn't work like that it's a special state
<nickchan>
but state 1 and above should be fine
<chadmed>
yeah its the same on the gpu aiui
<nickchan>
these registers also holds the amount of cores are allowed to be active in the cluster when that state is enter (boost state defs)
<chadmed>
anything that might help with pcluster idle power?