marcan changed the topic of #asahi to: Asahi Linux: porting Linux to Apple Silicon macs | General project discussion | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Topics: #asahi-dev #asahi-re #asahi-gpu #asahi-offtopic | Keep things on topic | Logs: https://alx.sh/l/asahi
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<sven> https://github.com/AsahiLinux/docs/wiki/HW:-Clocks alright, i believe i understand how clock-ids maps to clock-frequencies now
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<marcan> maz: is that kernel robot stuff from your m1-pcie tree something I need to worry about? I tried a ppc64 build here on my v4 branch and it seems to work fine
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<kettenis1> marcan: looks like that bot picked up a branch that it shouldn't
<kettenis1> related to pcie development
<kettenis1> speaking about pcie: I'm looking at the pcie tunables in m1n1
<kettenis1> two issues there:
<kettenis1> 1. to process some of the phy tunables I need to enable some clocks that are controlled by registers in the pcie block
<kettenis1> 2. the "fuse" tunables transplant some bits extracted from registers outside the pcie block (that are mentioned in the "reg" property of the pcie controller in the ADT) to some registers in the pcie block
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<kettenis1> at this point, the only reference I have for these is the correllium code
<kettenis1> is using what I learned from reading the corellium code ok, or do I need to wait for someone to re-RE those bits?
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