<dolphin>
feel free to pull in any relevant folks who might have opinions on the parasitic thread debugging vs. direct debugging
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<sima>
dolphin, mbrost already pinged me about this
<dolphin>
ah, ok, good. just returning from some time off so behind on mails
<sima>
I'll reply with some thoughts, but I think the main suggestion I'll drop is that maybe we should have a "how is gpu debugging supposed to work" doc section
<sima>
and collect acks from driver and probably more importantly, gdb folks
<sima>
otherwise I fear massive derail going to happen here
<sima>
also I think from the earlier parts of the thread, there's a confusion around "midlayer or not and what does it even mean"
<sima>
which I think would be good to document in ttm DOC: sections too
<sima>
at least I suggested mbrost to type up such a patch (but he's not around here rn)
<dolphin>
yeah, there definitely seem to be different layers to the discussion, I tried to answer the high level "why do this?"
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<sima>
dolphin, airlied replied
<dolphin>
I see your reply only?
<dolphin>
ah, probably add ":" there and it makes sense
<sima>
ah yes
<sima>
at least I didn't murder someone with missing punctuation :-P
<sima>
but was close, almost typed done instead of replied
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<dolphin>
but yeah, overall on the details I expect there of course will be plenty of discussion, but will be good to first understand if folks are aligned at the high level
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<Lynne>
its sad that the state of compute-only vulkan profiling is still exactly non-existent these days
<Lynne>
modifying mesa to dump anyway crashes the GPU, nvidia's tools are graphics-only
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<Lynne>
using clockrealtimeext is like threading a needle with an excavator
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* alyssa
doesn't understand derefs enough for this
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<karolherbst>
alyssa: yeah.. it's an annoying issue
<karolherbst>
the tldr is that various nir passes fight each other here
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<karolherbst>
we need to make passes smarter I think
<karolherbst>
like the issue in LLVM is, that everything is just a plain pointer, if you think of C based inheritance, then it's almost impossible to add the right cast
<karolherbst>
sometimes a field at offset 0 is used, sometimes the outer thing
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<karolherbst>
in that MR I _kinda_ tried to take into account how the pointer is used, but there are too many corner cases to do it sanely
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<alyssa>
what do we do
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<karolherbst>
I think we have to stop relying on the cast here. Maybe we should just assume it's alright, at least for CL and just trust the application isn't silly (tm), because data layouts are all well defined
<karolherbst>
the actual type of the source data doesn't actually matter with CL
<karolherbst>
but that's gonna be funky with the way we do derefs
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<karolherbst>
sadly that idea doesn't work well with scratch memory..
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<boratfromkz>
OK i post the last algorithm that made me smile again. after selecting a double value 72+72 you do +141+141 which comes from 1024-883 that line yields four times 72 and twice that of 69, now -883-26+512 of one triplet of two 72s and one 69, yields -184, where as another triplet when done with -840+512 yields -115 , so that should already say everything. I got it right this time. 26 comes
<boratfromkz>
from 1024-883-115. It is either some modified quadratics or synthetic division theorem way probably, but works immensely well on vectors that i was after. The science is so strong at my side that i do not bother with conflicts anymore, i figured all out, and i win all battles anyways without touching abusers in any way anymore. I fly that high. Scientists got the numbers correctly
<boratfromkz>
authored imo, i advise you to practice a bit and see yourself.
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<zf>
Is there a nice way I can dump the commands sent by mesa to the AMD GPU?
<zf>
(I'm getting visual corruption trying to decode H.264 with VA, but not with Vulkan, and staring at my own code several times has not helped me find where I'm filling parameters wrong, so I figure I might try attacking the problem from the other end)
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<karolherbst>
alyssa: the main issue is, that C has weird rules. Like you can have a temporary array of uint_8[128], but then always cast it to the same struct. Atm even if we make all those passes more intelligent, we'd fail to promote this to SSA values. And the issue you are seeing there is simply a specialized variant of that (where source and dest types are
<karolherbst>
somewhat related). I was considering a pass which works past IO lowering, but then if you have a single indirect, then that pass won't work anymore. But one thing we could do is, if we have a copy, we could try to introspect the incoming types and see if we could construct a path (with offset/idx 0) to the other (sub)type using deref_array and
<karolherbst>
deref_struct. Like if a is struct { float[4] } and the b is float[4], we simply replace a with deref_struct(a, 0). If a is struct { struct T t; float } and b is struct { struct T t; double }, we'd use deref_struct(..., 0) on both
<karolherbst>
just need to traverse the entire type chain probably
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<karolherbst>
and throw away more casts
<karolherbst>
so maybe just need to make the cast optimization smarter? mhhh
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<alyssa>
ok..
<alyssa>
karolherbst: is this going to go away when we switch to llvm's spirv backend?
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<karolherbst>
alyssa: maybe? At least we can enable optimization levels which might get rid of some of those things for us...
<karolherbst>
but that doesn't help anybody giving us spir-v from old tooling or something
<karolherbst>
maybe I'll take another look once I'm done with SVM or so
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<alyssa>
karolherbst: i'm not worried about spir-v in the wild
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<karolherbst>
right, but I am
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<karolherbst>
I really should try to figure out a good solution there, it's just not very critical in terms of functionality 🙃
<alyssa>
this is blocking far41 release, so.. it's critical for us at least..
<alyssa>
current plan is to backport the whole llvm18 stack..
<karolherbst>
ohh, is it crashing? Or simply "it requires scratch memory, but we don't handle that case"?
<alyssa>
the latter
<karolherbst>
right... Intel had the same issue, they just set scratch to 0 and moved one
<karolherbst>
*on
<alyssa>
no i mean
<alyssa>
load_scratch/store_scratch with llvm19 wasn't there with 18
<alyssa>
no asahi driver shaders need scratch or spilling, this is asserted
<karolherbst>
yeah, but intel has a backend pass to clean it up
<karolherbst>
so they opt to ssa a bit later
<jenatali>
Oh this is asahi's internal shaders, fun
<karolherbst>
but regardless of existing workarounds, I'd like to get it fixed at some point
<alyssa>
jenatali: yeah, although that's ultimately just a smoke test for cl being horribly broken or not
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<jenatali>
I mean, CL needs real scratch
<karolherbst>
maybe let me think about this issue this week and see if I come up with anything
<alyssa>
Yes, but if code didn't use scratch on fedora 40, it suddenly spilling is a severe perf regression
<jenatali>
Oh sure
<alyssa>
ultimately this is all a symptom of the LLVM SPIR-V circus
<karolherbst>
yeah... I think intel checks the offset and turns matching thing to an ssa value
<jenatali>
Yep
<karolherbst>
we could have a more generic pass for that, but that still keeps the core issue there
<karolherbst>
alyssa: I don't think the spir-v backend in llvm is gonna to change that, because the LLVM IR doesn't have that knowledge. The solution everybody goes for atm is just add more spir-v extensions 🙃
<alyssa>
i see.
<karolherbst>
and... that extension won't map nicely to nir anyway
<karolherbst>
I think
<jenatali>
karolherbst: I disagree. DXIL isn't going to support scratch, and the HLSL -> SPIR-V pipeline should also be capable of producing DXIL as part of the HLSL upstreaming
<karolherbst>
but in any case, I kinda wanted to solve this issue, because it's kinda fixable, just requires more code (tm)
<zf>
nowrep: does this look potentially correct? no idea if this is a driver bug or an application bug; VA is so underspecified...
<jenatali>
Folks are interested in getting Clang to produce graphics/Vulkan shaders, which have a lot more restrictions than CL
<jenatali>
This stuff will need to be solved before the SPIR-V layer for that to work
<karolherbst>
make "SPV_KHR_untyped_pointers" required in the next vulkan version, done
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<karolherbst>
or well.. it simply relies on SPV_KHR_untyped_pointers if you use LLVM to compile to vulkan spir-v
<karolherbst>
maybe I'm just less optimistic than you on that one :D
<nowrep>
zf: you should create the context with the coded size in the bitstream, so for h264 that's always 16 aligned
<zf>
hmm okay, and recreate it if it changes?
<zf>
the Vulkan side seems to be fine with this, but maybe that's a Vulkan (spec?) bug
<nowrep>
yeah recreate if the size changes
<zf>
should I also be recreating it for Vulkan? it seems to work fine as-is...
<nowrep>
yes
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<zf>
got it, thanks
<alyssa>
karolherbst: if perf is trash on all drivers, that's not going to fly :p
<karolherbst>
that's true, but I mean, we can fix this on a nir level, just have to make the optimizations smarter 🙃
<karolherbst>
generally the idea would be to be more relaxed comparing those two sides of copies (or load/stores) and figure out how to make it work.
<karolherbst>
alyssa: weird idea: try adding a padding member at offset 0 🙃 and see if that is a suitable workaround. I think that changes the generated code enough. But might end up with something similar
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<karolherbst>
mhh though in your case it's an array...
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<zf>
xrandr
<zf>
oops, wrong window :P
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<lina>
I worked out how to ship llvm18 spirv stuff on F41 so at least this isn't on fire any more ^^
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<dj-death>
alyssa: welcome to our world, I'm sorry.
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<karolherbst>
yeah.. I really should bump up the prio on that one 🙃
<figaroseen>
alyssa: they silence real people, if you want to preserve your work, you gonna have to cope with their rules and you might be as young that maybe it's beneficial to you, another plan would be since all real people are at my side including gangsters and real forces to make a meat out of this syndicate with my personal opinion there yes i would do it for personal reasons since they tried to
<figaroseen>
kill me, but for you i would not advise that path, just keep doing the nonsense work and have fun , maybe one day you get gifted some new ryzen or just buy one that works ok, the last eight generations of intel are also pretty ok. Those channels have turned into a joke anyhow to some degree the least, but most important the systems that can be redesigned have enough of base goodies to do
<figaroseen>
that. As for fact , windows, osx , linux and so many other oses, are suitable to make such hacks i have queued up.
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