#dri-devel on 2024-11-27 — irc logs at oftc.irclog.whitequark.org

2024-07-16 04:52 ChanServ changed the topic of #dri-devel to: <ajax> nothing involved with X should ever be unable to find a bar

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02:43 <benjaminl> is a correct reading of the view-local dependencies section of the vulkan spec that a view-local subpass dependency actually defines separate execution/memory dependencies for each view

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02:43 <benjaminl> and so sequences with viewmasks like 0b101 -> 0b010 -> 0b101 wouldn't create a dependency chain between the first subpass and the last subpass

02:44 <benjaminl> (while there would be a dependency chain without VIEW_LOCAL_BIT)

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05:32 <mareko> jenatali: any idea why d3d12 has assertion failures with this MR? https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31942 - https://gitlab.freedesktop.org/mesa/mesa/-/jobs/67264066

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05:35 <jenatali> mareko: Not offhand, and I won't be able to take a look this week since it's Thanksgiving :(

05:35 <jenatali> The I/O is the messiest part of that compiler for sure

05:35 <jenatali> I assume https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32047 doesn't fix it?

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09:47 <tursulin> airlied, sima: fyi there will be no drm-intel-next-fixes pull request this week, simply due absence of fixes

09:49 <airlied> tursulin: thanks for letting me know

09:50 <airlied> also I'll be doing any final rc1 pulls on my Friday morning (everyone's Thursday evening) and if anyone misses it'll be rc2

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10:45 <tarceri> dcbaker: yes please ignore that patch for backporting

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12:47 <Company> dj-death: random thing I noticed: on my Intel, GL_UNIFORM_BUFFER_OFFSET_ALIGNMENT is 32 and VkPhysicalDeviceLimits.minUniformBufferOffsetAlignment is 64. I was assuming those 2 numbers would be the same?

12:47 <Company> I just did a cross-check to make sure I'm querying the same limit in both and now I'm confused

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13:29 <dj-death> Company: yeah, that could likely be reduced

13:29 <Company> want me to file an issue about it?

13:31 <dj-death> Company: sure

13:31 <dj-death> Company: a0de2e0090535bd49b70c52917e7bdab628d354a is the change, it doesn't really explain why

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13:31 <dj-death> I mean cache issues

13:31 <dj-death> but those caching issues would more likely relate to buffer allocation

13:32 <dj-death> having them aligned to 64B is importatnt

13:32 <dj-death> otherwise different fixed function can step over each other's data

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13:58 <davestevenson> Asking again. Quick query for drm maintainers. I'm about to merge the vc4 series https://lore.kernel.org/linux-arm-kernel/20241025-drm-vc4-2712-support-v2-0-35efa83c8fc0@raspberrypi.com/. Do the dtbinding changes go through drm or dt tree? I'm still learning the processes.

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14:04 <Company> dj-death: it's https://gitlab.freedesktop.org/mesa/mesa/-/issues/12210 now

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14:06 <pinchartl> davestevenson: DT bindings changes that are bundled with DRM drivers can go through the DRM tree, once you get an ack from the DT maintainers

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14:10 <davestevenson> Thanks Laurent. I have the acks from DT maintainers, so I believe I'm good to go.

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14:54 <dj-death> Company: saw it

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16:28 <dcbaker> tarceri: thanks, will do

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