austriancoder changed the topic of #etnaviv to: #etnaviv - the home of the reverse-engineered Vivante GPU driver - Logs https://freenode.irclog.whitequark.org/etnaviv
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<FUZxxl> hello!
<FUZxxl> are there plans to support this driver on FreeBSD?
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<austriancoder> FUZxxl: not from my side - sorry
<FUZxxl> thanks
<FUZxxl> how unfortunate
<marex> austriancoder: oh hey
<marex> austriancoder: is there some documentation how to read the mmuv2 tables somewhere ?
<marex> austriancoder: I mean, I have the mmu.bin dump in front of me
<marex> the first 4k I guess is the MTLB
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<austriancoder> marex: the kernel driver should be a good starting point
<marex> austriancoder: the code is written so well, it is obvious and self-documenting ? :)
<marex> austriancoder: ok, so let me check this obvious-ness with you
<marex> austriancoder: so I got the devcoredump ... I run
<marex> ./dump/viv-unpack ~/etnaviv/new/devcoredump-20210405113612.bin | less
<marex> I get
<marex> 00000660 = 00000815 Cmd: [stall DMA: idle Fetch: valid] Req idle Cal idle
<marex> 00000668 = 48000000 FE fetched word 0
<marex> 0000066c = 00000701 FE fetched word 1
<marex> 00000664 = 00001138 Command DMA address
<marex> and
<marex> * 2 ring 00001000 00001000 4096
<marex> that asterisk tells me, that the problem is in ring
<marex> so
<marex> I run ... ./tools/dump_separate_cmdbuf.py -b ~/etnaviv/new/dump/ring.bin | less
<austriancoder> aha
<marex> and that tells me ... what ? I somehow need to get from that ... to the MMU fault address
<marex> that should be fd945000 I suppose ...
<marex> except there I have some .... gap ....
<marex> that I need filled
<marex> but from there, I dump the mmu.bin with hexdump -vC mmu.bin and assuming the fault address is 0xfd945000 , I get MTLB entry 0xff8 , so ...
<marex> 00000ff0 01 80 85 fb 01 40 85 fb 01 50 85 fb 01 60 85 fb |.....@...P...`..|
<marex> this ... ^^^^^^^^^^^
<marex> errr
<marex> correction
<marex> 00000000 01 30 85 fb 02 00 00 00 02 00 00 00 02 00 00 00 |.0..............|
<marex> *
<marex> 00000010 02 00 00 00 02 00 00 00 02 00 00 00 02 00 00 00 |................|
<marex> 00000fe0 01 30 86 fb 01 20 86 fb 01 f0 85 fb 01 70 85 fb |.0... .......p..|
<marex> 00000fd0 01 e0 ac fb 01 60 87 fb 01 40 86 fb 01 50 86 fb |.....`...@...P..|
<marex> 00000ff0 01 80 85 fb 01 40 85 fb 01 50 85 fb 01 60 85 fb |.....@...P...`..|
<marex> this ... so I have 13 entries populated in MTLB in total, the mmu.bin is 57344 which is 1+13 * 4096, OK
<austriancoder> give me 15 minutes and will be in front of a device with a keyboard
<marex> so the MTLB entry I have is #12 (the one before last) ...
<marex> and for 0xfd945000 the STLB entry offset should be 0x514, so ... this ?
<marex> 0000c510 05 a0 26 fb 05 b0 26 fb 05 c0 26 fb 05 d0 26 fb |..&...&...&...&.|
<marex> except the content makes little sense
<marex> my brain melts :)
<marex> austriancoder: what I dont understand is how we got from the ring dump to the MMU fault address and what are the MTLB entry values ; I understand the bottom 3 bits, not the rest
<marex> I guess that is PA of the TLB tables
<marex> *MMU tables
<marex> austriancoder: but that would mean that the MMU table entry is valid, and the GPU faults on valid populated MMU entry
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