austriancoder changed the topic of #etnaviv to: #etnaviv - the home of the reverse-engineered Vivante GPU driver - Logs https://freenode.irclog.whitequark.org/etnaviv
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<mntmn> [ 3.997703] etnaviv etnaviv: bound f0c0000.gpu (ops gpu_ops)
<mntmn> [ 4.003410] etnaviv-gpu f0c0000.gpu: model: GC7000, revision: 6202
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<marex> mntmn: congratulations ?
<mntmn> marex: well, i forgot how to do those headless render tests
<mntmn> also, i just disabled all clock enabling incl. core in the driver, so no idea if anything will happen
<marex> mntmn: well do you have some specific issue / question ?
<mntmn> marex: do you have a .c file that would do a headless render to a file?
<mntmn> because i don't have a display driver yet. afaik i need to port IMX8 HDP over
<marex> mntmn: er ... which SoC is that again ?
<marex> re headless rendering, hold on
<mntmn> marex: LS1028A
<mntmn> marex: thanks for the link, i will try this
<marex> mntmn: you _should_ be able to run at least dEQP and piglit headless too
<marex> mntmn: is that GPU the same as 8MQ or better ?
<mntmn> i think maybe worse
<mntmn> i have conflicting information. it is either GC7000L or GC7000UL
<marex> mntmn: new CPU for reform ?
<mntmn> yeah
<marex> 8mq isnt good enough ?
<marex> btw quad a72 would be nicer
<mntmn> there is no quad a72 with gpu
<mntmn> [ 2109.055839] etnaviv-gpu f0c0000.gpu: recover hung GPU!
<mntmn> marex: it isn't about "good enough". it's an alternative i'm exploring
<mntmn> ok so i guess it needs some kind of clock maybe.
<marex> mntmn: yep
<mntmn> the vivante driver has 3 register areas instead of one. the second one is phys_baseaddr (0x80000000). i wonder what that is
<mntmn> ddr base address viewed from the gpu?
<marex> mntmn: in DT ?
<mntmn> yep
<marex> does the driver use them ?
<marex> oh, this
<marex> reg = <0x0 0x38000000 0x0 0x8000>, <0x0 0x38008000 0x0 0x8000>,
<marex> <0x0 0x40000000 0x0 0x80000000>, <0x0 0x0 0x0 0x8000000>;
<marex> reg-names = "iobase_3d", "iobase_2d",
<marex> (from 8mm)
<marex> "phys_baseaddr", "contiguous_mem";
<mntmn> yes
<mntmn> it has phys_baseaddr and contiguous_mem as well
<mntmn> i guess the last one is just CMA
<marex> seems like DRAM to me, check the kernel part of the blob driver
<marex> it could be used for mapping textures in RAM for direct use by the GPU
<mntmn> currently looking for the LS linux sources to find the vendor dts... obviously i had it at some point but forgot
<cphealy> mntmn: With the LS1028A, is the ARM Mali Display Controller working?
<mntmn> cphealy: i think so, but that's not enough. it also needs imx8 hdp
<cphealy> ack
<cphealy> Regarding conflicting information for GC7000L or GC7000UL, can you share what the conflicting information is? Last time I looked, I was under the impression that it was something lighter weight than the GC7000L.
<mntmn> i will get back to that later, i'm currently poking in files
<cphealy> BTW, with the LS1028A, it uses the ARM CCI-400. With this interconnect IP core, you should be able to enable CONFIG_ARM_CCI400_PMU in the kernel config and be able to see bus master usage by each bus master including the 3D GPU.
<mntmn> thanks, enabling it
<cphealy> You'll want to have the "perf" tool in your rootfs to access the CCI-400 HW counters too.
<marex> mntmn: seems the clock are always on
<marex> mntmn: how does your GPU node look like in your DT ?
<mntmn> marex: my node looks like the vendor one
<mntmn> ah yeah, in the vivante hal driver, in case of ls1028a, the driver removes all the clock and power operations
<mntmn> gpu is not firing any interrupts
<marex> mntmn: just keep the first entry in regs, should be enough
<mntmn> ok, that won't make it work though
<marex> mntmn: why ? :)
<marex> mntmn: one step at a time
<mntmn> the registers are already fine?
<mntmn> i mean, the gpu wouldn't be detected otherwise?
<marex> mntmn: probably
<marex> mntmn: is there some firmware which might be configuring/enabling clock ?
<mntmn> hmm, unsure... i'm using vendor u-boot and loading hdp firmware
<marex> mntmn: aarch64 has mandatory PSCI implementation, so what implements that on your machine ?
<mntmn> probably something that's blobbed together with the bootloader?
<marex> u-boot is GPL
<mntmn> well, on imx8mq the hdmi and ddr4 firmwares, which are blobs, are glued together with u-boot
<mntmn> well, well. i really need to go home to sleep.
<mntmn> > Add two 1500Mhz cpu frequency for emmc and sd boot rcw.
<mntmn> In those rcws, gpu is running at 600Mhz.
<mntmn> this is especially interesting because max cpu freq was specced at 1.3ghz, not 1.5ghz
<mntmn> also looks like the clocks, including GPU, are configured via RCW
<marex> I have to admit, I wonder whether bundling the blobs into flash.bin with U-Boot might be considered linking
<marex> because if so, that would mean NXP might have to release the blob sources
<marex> like that's gonna happen tho
<mntmn> marex: ha :D
<mntmn> lawyer up...
<marex> heh
<marex> what is rcw ?
<marex> read-change-write ?
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<cphealy> Regarding GPU frequency, from what I see, the max frequency can be different based on part number.
<mntmn> marex: reset configuration word
<mntmn> CGA_PLL2_RAT controls the gpu freq
<marex> mntmn: oh hum
<marex> mntmn: well is it enabled and locked ?
<mntmn> i don't know. that is magic rcw stuff
<mntmn> but i can check if i see anything about CGA_PLL2 in the kernel
<mntmn> ah that is clk-qoriq
<cphealy> According to the LS1028A datasheet, the GPU can be run at speeds up to 700Mhz.
<mntmn> yep
<mntmn> ok enough for today. n8n8
<cphealy> If the DTSI sets the GPU at a frequency lower than the datasheet, this is not too much of a surprise. The i.MX8M was similar in that the vendor DTSI set the GPU frequency to 800MHz while the datasheet said 1GHz was the max. With a design I worked on, we ran the 3D GPU at 1GHz with no issue, but we did have a very good thermal design with the board.
<mntmn> cphealy: on ls1028a, gpu clocks are not in the dtsi. it is configured via rcw.