<lumag_>
abhinav___, feel free to include my r-b when you will submit this change :-D
<robclark>
abhinav___: lm state matches in both cases
<robclark>
abhinav___: btw, for the regs that are double-buffered (ie. latch of flush+vblank), do the unbuffered values show up anywhere in the I/O space (ie. if it was a flush issue, would it show up in register dumps)?
<sboyd>
is there a flush harder button?
<abhinav___>
robclark: so in other words you are asking if a particular register value is not flushed will it show stale value or the new one when you read? It will show the new value in the I/O state but HW will be using the old value till the flush
<abhinav___>
sboyd: :)
<robclark>
abhinav___: I meant is there another register that shows the flushed/latched value..
<abhinav___>
robclark: no, there isnt such one
<robclark>
hmm, ok.. that would have been useful to debug flush issues (but at least I don't *think* that is what this is)
<abhinav___>
yeah i also dont think so ..... i think the solid fill on the planes will give some answer
<abhinav___>
we will try to fix up that path in the bug
<abhinav___>
will leave a note to kalyan tonight
<robclark>
sg
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<aka_[m]>
Do anyone have idea what and if something should be set inside bw_table of venus/core.c for avg_10bit if downstream vidc.dtsi doesnt contain ubwc-10bit profile? i only has ubwc on 8953/8937