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<arnd>
bamse: a number of bugfixes in your "Qualcomm driver updates for v5.18" branch look like they should be in v5.17 and backports instead, e.g. 0ee30ace67e4 ("cpuidle: qcom-spm: Check if any CPU is managed by SPM") or 8030cb9a5568 ("soc: qcom: aoss: remove spurious IRQF_ONESHOT flags")
<arnd>
I've held off on the branch for the moment, please let me know if you can do a quick respin, or if I should merge the version you sent as-is
<arnd>
I'll be on vacation tomorrow until the rest of this week, and would like to have the bulk of the merges done by tonight, but I know gregkh is annoyed by having to backport patches that look urgent but only make it in during the merge window
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<arnd>
bamse: it looks like you did not resend the three SM8450 defconfig patches that failed to make it into v5.17. Should I just cherry-pick them from the old branch?
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<bamse>
arnd: iiuc, the spm change comes into play when we're booting e.g. 8916 in 32-bit mode, which relates to some of the other patches, so this isn't a problem in practice until 5.18
<bamse>
arnd: the aoss fix sounds like a bug fix, but i've not heard anyone report issues with that...so i would prefer not having to revert and move it to the fixes branch...
<bamse>
arnd: so please just merge those as is
<bamse>
arnd: the 8450 defconfig updates would make it possible to boot the qrd (reference device), so having those on 5.17 would be cool, but that said, 8450 is actively being developed, so anyone really interested in "running" upstream will follow on to 5.18-rc1 etc...so either way is fine with me
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<arnd>
bamse: ok, thanks for taking another look, I've merged it all for 5.18 now
<arnd>
I'm still unsure about the SPM commit 0ee30ace67e4 though, from my reading, this doesn't as much impact qualcomm SoCs as it does non-qualcomm SoCs when running a cross-platform distro kernel
<arnd>
bamse: do you have a pointer to what's going on with 32-bit mode on 8916? I thought people stopped doing that long ago
<minecrell>
arnd: There are some 8916 devices that can only boot arm32 (EL3 firmware is 32-bit). Not much can be done for those thanks to secure boot and vendors using ancient firmware...
<minecrell>
arnd: and yes, the SPM fix is mainly for non-qcom platforms although it's mostly cosmetic
<bamse>
hmm, you're right...seems like we've been creating that platform_device everywhere and i presume all other platforms end up EPROBE_DEFER'ing on qcom_scm not being present
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<bamse>
minecrell: but afaict it's not a regression, just something that everyone else should have wanted for a long time?
<Mis012[m]>
strictly speaking if we find a way to get code execution from the hypervisor (should have code exec on hypervisor on 8916, right?), then we can sidestep this problem ;)
<Mis012[m]>
and just because the hw allows for protecting TZ from HYP and even vice versa, doesn't mean it's all that likely that it's being done properly in qcom's quality sw is it :P
<minecrell>
Mis012[m]: no you can't, since you cannot have a 64-bit EL2 with 32-bit EL3 either
<Mis012[m]>
well, I'd assume 32bit EL2 has the same bug?
<Mis012[m]>
*hyp
<minecrell>
which bug?
<Mis012[m]>
they hypervisor code execution bug?
<minecrell>
My point is: it doesn't help solve the 32-bit-only problem
<Mis012[m]>
well, it does in a way
<minecrell>
how?
<Mis012[m]>
there was not likely much testing for hyp->EL3 code execution back then?
<minecrell>
ah, you want to do another privilege escalation to EL3?
<Mis012[m]>
seems like the logical next step /s
<Mis012[m]>
the so-called EL+1 induction
<Mis012[m]>
I mean, fwiw I haven't checked if qcom's TZ bloat manages to fit into secure EL2 and EL1, but I doubt it :P
<minecrell>
While the hypervisor is pretty stupid on 8916, I doubt that TZ is, qcom had plenty of years to polish that. Having EL2 doesn't really help you to gain access to EL3 on 8916, since TZ memory is protected by extra hw components, not some mechanism in the ARM CPUs
<Mis012[m]>
well, my thought process was more along the lines of hyp-restricted SCM calls
<minecrell>
I doubt anything like that exists at all
<minecrell>
on 8916 at least
<minecrell>
the hyp there simply seems so infinitely useless
<Mis012[m]>
it's probably equally useless everywhere, the only thing that varies is the amount of code that you now need to put somewhere else :P
<Mis012[m]>
there is no real reason that you need that code to run in EL2 other than it presumably makes it quite a bit easier to have special access permissions for that code
<Mis012[m]>
minecrell: out of curiosity, what is the TZ BSP version on your 32bit sammy?
<Mis012[m]>
it better be very old if they couldn't just use 64bit...
<minecrell>
Mis012[m]: I think Android 4.4 didn't have 64-bit support yet so the TZ shipped with that Android version was usually 32-bit
<minecrell>
and this Samsung device was specifically designed to never receive an update, in fact I think they even released it after Android 5.0 was already out
<minecrell>
TZ.BF.2.5.3-00015
<Mis012[m]>
dammit, that's > TZ.BF.2.5.1
<Mis012[m]>
and TZ.BF.2.5.1 was by my guesstimation some time before they found all the buffer overflow issues
<Mis012[m]>
minecrell: actually isn't there a sahara bug on 8916?
<minecrell>
Mis012[m]: I've read that it is possible to boot arbitrary programmers on 8916, but I've yet to find someone who knows how to do that
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<calebccff>
It should supported PMICs with only one USID now, still need to test and cleanup
<calebccff>
however I can't find a way to support a PMIC with more than 2 USIDs - not without modifying DT at least
<calebccff>
does this seem reasonable?
<calebccff>
(not sure what Dmitry's IRC nick is to ping him here)
<bamse>
calebccff: dmitry is lumag_
<calebccff>
ah! thanks
<bamse>
calebccff: and i was certain that the pmics all occupied 2 usids...not sure what to do about that...
<calebccff>
heh, yeah, it's not too bad, supporting 1 or 2 is easy enough, and I've done some extra rework to make it easier to extend in the future. Supporting more than 2 requires knowing which (relative to the PMIC) USID you're in so you can walk to the base USID
<calebccff>
ah actually i guess you can walk backwards until you find the USID with the PMIC revid struct populated
<calebccff>
there's no of_ helper for walking backwards though -_-
<bamse>
i'm not sure i understand how the addresses are composed...
<bamse>
in the hardware documentation registers are typically 17 bits, and the top bit becomes the lsb in the usid
<bamse>
that's why i wonder how this translates to the "new" case
<calebccff>
bamse: hm, so with that addressing scheme you can't have more than 2 USIDs right?
<bamse>
calebccff: well...that depends on how those bits actually "spill"
<bamse>
calebccff: i don't remember how the addressing works...
<calebccff>
bamse: are there any public SPMI docs?
<bamse>
i don't think so
<calebccff>
given we currently don't have any PMICs with more than 2 USIDs in mainline perhaps it's fine to leave it with that restriction and add a WARN if someone adds a PMIC with more than 2 USIDs and tries to call the function
<bamse>
but how do you distinguish one pmic with two usids from two pmics with one usid?
<calebccff>
the number of PMICs is specified in the DT match data as suggested by lumag