<wfranken[m]>
No, unfortunately this device does not have any device tree downstream, only board files. But I used that as documentation for the panel driver.
<Mis012[m]>
I wouldn't be too surprised if it turned out that the board file version of the panel dtsi is generated from the same xml...
<Mis012[m]>
and I think there was some work on applying lmdpdg to lk1st panel "drivers", which are also generated from that xml
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<wfranken[m]>
Downstream driver says something about turning up the MDP clocks frequency to avoid DSI underflows, is there a way to do that in mainline?
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<aka_[m]>
On mainline it always spam that lack of interconnect migjt make display under flow
<aka_[m]>
It seems to force pclk rate
<aka_[m]>
To 35000000
<wfranken[m]>
<aka_[m]> "On mainline it always spam..." <- Yes, I was concerned about that too. Might need to invest some more time to add interconnect driver for this soc.
<wfranken[m]>
<aka_[m]> "To 35000000" <- Ok, can try something like that.
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<Mis012[m]>
seems I don't have a FLAT for that one :/
<wfranken[m]>
<aka_[m]> "To 35000000" <- Or you meant that on mainline the pclk is forced to 35000000? Where does it do that?