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<MoeIcenowy> smaeul: hacked D1 libdram to let it contain no Xthead instr
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<smaeul> MoeIcenowy: oh, good! does that mean the whole SPL now runs without enabling Xthead?
<smaeul> and if you are interested, please send a PR to https://github.com/smaeul/sun20i_d1_spl
<MoeIcenowy> well I think some cache code still uses Xthead
<MoeIcenowy> BTW just disabling MAEE seems to be not enough to allow kernel w/o MMU extension to run
<MoeIcenowy> (MAEE is the switch of MMU extension in mxstatus reg
<smaeul> do you mean it still traps when enabling the MMU?
<MoeIcenowy> I got a few lines of earlyprintk, and then trap
<MoeIcenowy> BTW the cache instruction may get replaced by an operation to MCOR reg
<smaeul> well a few lines is more than I was expecting. I wonder if the bus non-coherency breaks even UART
<smaeul> maybe it will work if you globally disable the data cache
<MoeIcenowy> BTW I cleanup Xthead mainly to ease Ghidra
<smaeul> ah, the fun part :)
<smaeul> were you able to make use of any of the DWARF info?
<MoeIcenowy> well, at least type info
<MoeIcenowy> and now I have experience on R329/V831 DRAM ;-)
<smaeul> does it look similar?
<smaeul> anyway, good luck on the reversint!
<smaeul> *reversing
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<swiftgeek> I feel like my HDMI issues are coming from HPD handling
<swiftgeek> but instead of fixing software, I think I will just pull it up permanently
<swiftgeek> on monitor side
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<swiftgeek> k, it's floating inside
<swiftgeek> HDMI calls for 1kΩ so i will go with that
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<swiftgeek> yep, that was it
<swiftgeek> but u-boot still doesn't like it lol
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<swiftgeek> ok kicked in now for some reason
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<swiftgeek> actually now older intel does not like it
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<smaeul> I'm going down the rabbit hole of PINCTRL/DM_GPIO conversion, and there actually is some non-SPL use of legacy I2C (grep for CONFIG_VIDEO_LCD_I2C_BUS)
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<smaeul> I'll send a patch for this
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