ChanServ changed the topic of #panfrost to: Panfrost - FLOSS Mali Midgard & Bifrost - Logs https://oftc.irclog.whitequark.org/panfrost - <macc24> i have been here before it was popular
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<icecream95> I'm getting some really weird results when testing uploads to WC memory on duet:
<icecream95> For example, memset backwards byte-by-byte usually gets 361 MB/s, but sometimes it does it at 1215 MB/s
<icecream95> CCI/cpufreq are supposedly at "performance". It oscillates between the two rates for the same BO, so it's not related to memory placement
<icecream95> This reminds me of the RK3288 "twice as fast on core 0" bug, which is probably still unsolved
<HdkR> tasksetting doesn't lock in behaviour?
<icecream95> Am using already using taskset
<HdkR> AArch64?
<icecream95> yes
<icecream95> it happens for both big and little cores; LITTLE gets 281 / 626 MB/s
<HdkR> You could try DC ZVA and see if it oscillates the same way
<HdkR> Although that isn't a backwards memset :P
<icecream95> If I use malloc()'d memory rather than a BO, it always copies at the slower rate
<icecream95> (for big cores, little cores still go back and forth..)
<HdkR> SoC quirks? :)
<icecream95> If I decrease the memory size from 16MB to 16MB - 64 bytes, then it always runs at 945 MB/s, so it looks like weird caching interactions?
<icecream95> Oh great, now my *other* test function is showing the weird behaviour. Maybe that one needs an extra free cache-line?
<HdkR> Only happens on backwards memset as well, not forwards?
<icecream95> the other function was going forwards
<HdkR> ah
<HdkR> Are they just a loop decrementing a counter and doing single byte stores?
<icecream95> yep
<HdkR> Have you checked if your loop alignment is changing behaviour?
* icecream95 inserts an .align directive
<HdkR> I believe Cortex wants either 16 or 32byte alignment for optimal loops
<icecream95> that doesn't seem to have much of an affect
<HdkR> womp womp
<HdkR> Maybe the SoC has a quirk where if you flood the system with 8bit memory accesses it can fall on its face :P
<HdkR> Not many implementations of memset would just do 8bit stores afterall
* icecream95 finds that perf stat only works properly on the little cores
<icecream95> Oh, don't tell me I was just measuring time wrong!
<icecream95> Well, that was a fun waste of time...
<HdkR> oops!
<icecream95> That reminds me to check whether the kernel allows reading the cycle counter from userspace on AArch64..
<HdkR> The virtual cycle counter always
<HdkR> CNTVCT_EL0 is always available, even on Android where they do a fault dance for no reason
<HdkR> Just make sure to also read CNTFRQ_EL0 later so you know what the frequency is when calculating time :)
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<cphealy> icecream95: for this issue, can you look at the cache HW counters on the ARM or GPU side to see if it gives any clues?
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