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<marcan>
maz: please correct me if I'm wrong re my conclusion from today's stream of pain
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<marcan>
if I'm implementing an irqchip, its ops will be called inside a raw_spinlock
<marcan>
if those ops rely on a shared resource that has to be serialized, that means that shared resource must be protected by a raw_spinlock
<marcan>
which means everything involved in handling that resource can only use raw_spinlocks
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<marcan>
... because I need IRQ support for SMC GPIOs, which means I'm implementing a *remote irqchip* running on another CPU, communicating via mailbox messages, over a shared serialized message transport shared with a pile of other drivers.
<marcan>
and apparently you aren't even allowed to allocate GFP_ATOMIC inside such a spinlock
<sven>
huh, aren't there irqchips that need to talke to some i2c device to mask/unask/etc?
<maz>
marcan: if you want the irqchip to be totally synchronous, then you are right. but what you describe looks a lot more like an i2c (or other 'slow bus' protocol).
<maz>
... i2c irqchip of some sort
<marcan>
is that a thing and how does it work?
<maz>
it is a thing. you just end-up with an irq thread that deals with the irqchip itself.
<maz>
look at how i2c GPIO expanders deal with interrupts.
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<marcan>
oh, the bus_lock/bus_sync_unlock thing?
<marcan>
well, that was a waste of several hours today then...
<marcan>
still, very tempted to burn mailbox in flames after today
<sven>
:D
<marcan>
maz: have you seen the discussion re pcie power? that's what I wanted to get to today, but it ended up all being about SMC GPIO IRQs in the end...
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<maz>
marcan: I saw the discussion, and decided that I had better ways of wasting my time. I'm really annoyed by the fact that what works for one platform cannot be used for another.
<marcan>
dunno if you saw the last email I sent; I think keeping it the way it is now makes sense, except maybe using a regulator instead of a gpio since it's more generic for power supplies
<marcan>
and then I can implement it as d3cold in apcie and support that
<maz>
I'm still behind on email (and still jet-lagged). I'll have a look.
<marcan>
thanks :)
<kettenis>
marcan: can you try to remember to add me to that pci thread on your next reply
<marcan>
ack
<marcan>
sven: ok, it works fine with that bus_lock magic, without requiring atomic context
<marcan>
that means the only change to rtkit is removing that broken wait function
<kettenis>
better
<kettenis>
marcan: what was the motivation for the cpufreq compatible rename?
<sven>
I guess we can send that as a follow up patch anyway.
<marcan>
mostly that it's not a single cluster any more, now that a single instance handles all clusters
<marcan>
I can leave the old compatible in for you for a while if you want
<sven>
and nice that it works now :-)
<kettenis>
marcan: that might be a good idea, although cpufreq isn't essential
<sven>
ohhhhh…. I also just realized that I never sent out that PR because I confused myself with the test mail I just sent to myself *sigh*
<marcan>
heh :)
<kettenis>
keeping the old compatible would give folks installing OpenBSD 7.1 using an updated Asahi Installer a better experience
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<marcan>
pushed what I have so far to pcie/wip-sd-pm if anyone wants to look
<marcan>
also added CD debouncing which also makes the insertion more reliable, because apparently these sockets are noncompliant..
<j`ey>
marcan: that mailbox flush change...
<marcan>
and I might do it differently too...
<marcan>
need to see what other drivers are doing there