ChanServ changed the topic of #asahi-dev to: Asahi Linux: porting Linux to Apple Silicon macs | Non-development talk: #asahi | General development | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-dev
<jannau>
no, they're not in the live ADT as read from the device. We wondered about that during M1 Max bringup and marcan asked on twitter if anyone had M1 Max with ane1 but nobody did
<jannau>
not sure why but apple seems to have decided not use ane1
<eiln_>
jannau: the nodes are in driver strings & iboot loads the firmware. some last minute mishap ig
<eiln_>
m2 max shoulve had ane1 by trends, but it only has ane0
<jannau>
iirc we tried to power it up and access its mmio space but it was completely fused off
<eiln_>
ane0/ane1 have near identical fw, maybe overheating?
<marcan>
eiln_: I think they decided not to ever enable it for power delivery/product reasons
<marcan>
m2 max does not have ane1 physically, it is not present in the die
<marcan>
so the double ane for max models was a planned feature that got cut and removed from the next iteration
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<marcan>
I'm sure they had some test hardware somewhere with it enabled, but they never shipped it
<marcan>
ane is actually quite power hungry, it's a major component in the CLPC stuff and has its own power rail, so ane1 is probably not even wired to power on any machine
<eiln_>
interestingly t8103 ane & t6000 ane compile the same microseq
<eiln_>
they share a unified -h13 flag
<eiln_>
ane/ane0 fw is rlly similar too, i highly doubt ane0/ane1 had mem sharing features
<marcan>
the firmwares are all different for stupid reasons
<marcan>
e.g. ane0 and ane2 have different firmware even though they are literally the same hardware
<marcan>
the first difference I see is different MMIO addresses (duh)
<eiln_>
its bc of mmio base address lol
<dottedmag>
marcan: Yes, I'll talk to daniels
<marcan>
but actually ane1 and ane2 are almost identical in .text, then .data changes
<marcan>
ane0 and ane2 are more different
<eiln_>
ig stacking two ane's didn't go as planned
<marcan>
so that makes me think ane0 may have some other subtle difference (or maybe not and it's just ARM instruction encoding gave a different instruction count when they changed the base addr)
<marcan>
but since ane1 and ane2 are basically the same, no reason to believe ane1 is different in any way
<marcan>
they just dropped it
<eiln_>
they can't utilize ane1 to 2x one job bc they have separate L2s. nothing suggests the two can communicate actually. so at most it 2x two jobs simultaenously
<marcan>
yup
<jannau>
povik: https://tpaste.us/PEQ1 looks good. I discovered I even need it for dcpext. I suppose pci was the only thing without runtime pm when I looked at it. dcp is shielded from the dart_hw_reset since the involved darts are locked. dart-dispext* is not locked and that started to cause problems
<marcan>
it's just a copy paste and they decided it wasn't worth it
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<jannau>
dcpext on m2 half working. dcpext is happy but the display is not and claims there's no signal
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<jannau>
I guess an issue in atc-phy putting the dp signals on the wires
<jannau>
FIFO_RD_UNK_EN in the atc-dpxbar has for some reason a different field layout and uses 4 bits instead of 2 per dispext
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<jannau>
might actually be a software issue, there's for some reason no modeset
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<jannau>
sigh, entirely an software issue. the iommu grouping doesn't work. the fb mappings are all on disp0-dart and none are on dispext0-dart
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<jannau>
sigh, all the disp* darts on m2 have locked tcr/ttbr out of iboot. the current lcoked dart handling can only deal with a single locked dart in group
<eiln_>
and attach the mon.poll() results if some PD_COUNT val works
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<jannau>
finally a picture with dcpext on the m2 mac mini. I unfortunately can't make any nice pictures since the pcie xhci dies and I have no input devices
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