ChanServ changed the topic of #asahi-dev to: Asahi Linux: porting Linux to Apple Silicon macs | Non-development talk: #asahi | General development | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-dev
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<nickchan> any particularly reason why system level cache is not listed in dts file for M1?
<nickchan> only l1 and l2 listed
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<nickchan> amazing macOS has pmu definitions for Apple A7
<nicolas17> nickchan: btw if you ever feel like writing docs, I think more technical hardware info is totally in scope for theapplewiki ;)
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<nickchan> okay i don't really know what I am doing but i am going to add a11 pmu into the dts and see whatever happens
<nickchan> no
<nickchan> i should generate A7 definitions first and see how different it is from m1
<nickchan> Ugh
<nickchan> there's some events on m1 that's not on a7 (expected)
<nickchan> however some affinities are different
<nickchan> nevermind i messed something up the definitions are very different
<nickchan> whatever definitely need per-implementation tables now
<nickchan> trying to see how to refractor m1_pmu_get_event_idx()
<nickchan> problem is I need somewhere to store the type of the pmu
<nickchan> other than trying to comparing the pmu name string
<nickchan> alternatively somewhere to store a pointer to the affinity table for the pmu
<nickchan> I could use the platform_device's data
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<nickchan> when i try to generate perf patches with gen_perf_patch.py, only a14 and above worked
<nickchan> a13 and below is empty for some reason
<nickchan> gen_driver.py works however
<nickchan> okay let's try update mapfile.py
<nickchan> okay that worked
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<nickchan> now I need a way to test the pmu
<nickchan> somehow
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<nickchan> okay no I can't stash the table in the driver data of cpupmu->plat_device
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<nickchan> nevermind I will just redefine m1_pmu_get_event_idx for every table
<nickchan> okay got perf stat to work
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<nickchan> a9 has 8 counters only
<nickchan> a10 already has 10 counters
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<nickchan> a7 still has 8 counters
<nickchan> it can report instructions and cycles so it works
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<nickchan> in summary:
<nickchan> - overall pmu logic is same all the way back to a7
<nickchan> - a7 - a9 has 8 counters, a10-m1 has 10 counters
<nickchan> - the available events and affinities are different
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<nickchan> and I probably should check out what happens with A32 EL0...
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<nickchan> added A32 EL0 counting support in m1_pmu_configure_counter() but numbers on A7 still seems off (A8-A9) seems normal
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<nickchan> okay here's a problem it turns out that A32 and A64 instructions uses different pmu events
<nickchan> and T32 instructions has another pmu event
<nickchan> so there's no all instruction hw event
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<nickchan> appearently
<nickchan> a7-a10's CPU PMU does not have the interrupt fired via FIQ
<nickchan> and uses PMCR0_IMODE_AIC instead of PMCR0_IMODE_FIQ
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