marcan changed the topic of #asahi-gpu to: Asahi Linux GPU development (no user support, NO binary reversing) | Keep things on topic | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-gpu
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<alyssa> dougall: <disassembly failed>, ooo, fun
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<alyssa> 5905 0000 103c 8000
<alyssa> seen with zs_emit + multisampling
<alyssa> from context, looks like it must set r1 to the mask of active samples
<alyssa> pretty weird loop getting emitted, calling zs_emit on 8 samples at a time
<alyssa> indicating compiler support for MSAA 16x?!
<alyssa> that's the only way I can read this that makes sense
<alyssa> if I don't have any references to per-sample stuff it doesn't do that silliness
<alyssa> though it has other silliness. delight
<alyssa> meh let's implement the obvious thing in Mesa and see if anything breaks
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<alyssa> Pass (Pass)
<alyssa> Eyyy
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<alyssa> lina: I'm pretty confused .. I don't see any mechanism for rendering into depth stencil miptrees
<alyssa> We just specify the size and the base address for twiddled
<alyssa> that's fine for power-of-two and for levle 0
<alyssa> but the hw has no way to know whether it needs to add the padding silliness
<alyssa> for colour render targets, there's a dedicated "level" field in the PBE descriptor and the width/height are of level 0
<alyssa> for depth/stencil, Metal is just setting the width/height to that of the rendered level
<alyssa> and setting the base address
<alyssa> so how does the hw know to insert padding?
<alyssa> am I missing something silly here?
<alyssa> is AGX broken?!
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<alyssa> like, I'm looking at traces from Metal and i can't see how this can possibly be correct
<alyssa> yeah, I can't see how this can possibly work
<alyssa> rendering to 16x16 vs 32x32 (level=1) vs 33x33 (level=1) looks the same
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<alyssa> unless twiddling for depth/stencil formats is weirdly different from colour
<alyssa> which is... possible but unlikely because that would complicate sampling...
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<alyssa> and I have weak evidence against that idea as well
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<eiln_> Hello! slightly off topic but was pointed to here
<eiln_> My name is Eileen and my handles use @eiln typically.
<eiln_> I've made progress with the GPU's younger sister, i.e. Apple Neural Engine / ANE / NPU
<eiln_> My work is on
<eiln_> I develop on github but am currently having issues it's a mirror
<eiln_> TDLR: ane is a low precision (fp16) configurable mac circuit really good for chained/fifo stream number crunching
<eiln_> I've got the kernel side / work interface / tiling pretty much down, so the only barrier to all those exotic ops are the compiler output ("regfile" that gets dma'd to configuration registers). I do have prototypes for elementwise add/mul/min/max, 2d convolution, and batched matrix multiplications, but it's still largely a mystery.
<eiln_> Being a non-essential component and without much precedent, I feel pretty lost on what direction to head with development. I would rather asahi leverage the hardware to its own needs, not replicate apple's model (which i find very questionable anyway). Hence I currently have no idea of what a final product would even look like (e.g., support what? does it go under drm?). I'm looking for any form of advice / guidance.
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<eiln_> figured this introduction from their patents may be helpful:
<eiln_> "Neural processor circuit 218 is a circuit that performs various machine learning operations based on computation including multiplication , addition , and accumulation . Neural processor circuit 218 is a configurable circuit that performs these operations in a fast and power -efficient manner while relieving CPU 208 of resource - intensive operations associated with neural network operations.
<eiln_> Neural processor circuit 218 may receive the input data from sensor interface 212 , the image signal processor 206 , persistent storage 228 , system memory 230 or other sources such as network interface 210 or GPU 220"
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<marcan> eiln_: I'm a bit confused about the ASC though; I know it has a big firmware blob but it doesn't look like it uses the usual mailbox RTKit interface? Does it have some bespoke interface?
<marcan> eiln_: also I think your "pmgr" tunables are actually fabric tunables, see the analogous https://github.com/AsahiLinux/m1n1/blob/lina/gpu-wip/src/tunables_static.c#L22 from lina's stuff
<eiln_> ah hv said pmgr node so it's what i assumed. i've added a patch under tunables_static.c too
<eiln_> regarding asc, sigh
<marcan> and your "dart tunables" are DAPF, see dapf.c in m1n1 (this is already implemented)
<marcan> they are mostly likely dynamic and depend on the firmware version and RAM config of the device
<marcan> since they probably map the firmware
<sven> pmgr often is apple‘s „let’s stuff things that don’t fit anywhere else“
<eiln_> asc is completely separate from the engine circuitry. the dma they refer to isn't asc-emulated-dma
<marcan> you probably just need to call p.dapf_init("/arm-io/dart-ane")
<marcan> eiln_: that's typical yes, the ASCs sit on the side. but does macOS talk to the engine directly, or to the ASC?
<marcan> usually everything goes through the ASC for hardware that has an ASC
<eiln_> asc is only responsible for queue stacking, which i replicate in TaskManager
<marcan> so you don't really use the asc, just talk to the hardware directly?
<eiln_> sigh, the ane-asc init process is a 9-step process, and i've been stuck at stage 8
<eiln_> so i copied the reg diffs to "fill in"
<eiln_> yes the asc isn't even turned on
<eiln_> specifically enqueue_tq
<eiln_> and the 3 reg writes in execute_tq
<eiln_> are asc duties
<eiln_> given i have rvbar & the asc init code technically i can write my own fw to do just that
<marcan> so what does the rest of the 3MB of firmware do? :p
<marcan> (I'm just trying to understand this)
<eiln_> props up an entire server with isp
<eiln_> i'm pretty certain that my asc init is stuck @ stage 8 because isp isn't
<eiln_> there's a "program" abstraction that's really just BAR (in ane_context.py)
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<marcan> oh. isp as in the camera thing?
<eiln_> yes
<marcan> so isp and ane talk to each other for the ML stuff in the camera processing?
<eiln_> unless explicitly turned off with boot-args, the first ane init is called by isp
<eiln_> i believe isp has an ane node?
<marcan> that sounds like we eventually need to figure out how to make it work then, unless ISP can be told not to talk to ANE
<marcan> since we kind of need ISP to work...
<eiln_> i don't know if isp depends on ane though
<marcan> what happens on devices without ISP?
<marcan> i.e. desktops
<eiln_> no idea, i only have a t8103
<eiln_> there's a ane_isp.afpp file somewhere
<marcan> I mean t8103 is in desktops (mac mini)
<marcan> isp has function-ane_ep_control = 329:eCtl()
<marcan> and function-ane_data_param_set = 329:dSet()
<marcan> and function-ane_data_param_get = 329:dGet()
<marcan> I guess it brokers through that?
<eiln_> that looks like segment-ranges
<marcan> those are Apple ARM function calls
<marcan> they're one way apple connects drivers together
<marcan> by pointing them at sort of marshalled functions in other device nodes
<marcan> segment-ranges is just the firmware
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<eiln_> to be honest I really don't know much about isp
<eiln_> the main guy behind the ane patents used to do isp
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<eiln_> i also know one of them sets up a ring buffer endpt
<eiln_> which isn't in the ane mmio range
<eiln_> and i traced with boot-args
<eiln_> camEnableAneIsp=0 camEnableAneIspAfpp=0
<eiln_> for this exact reason
<marcan> sounds like we might need some coordination with the person reversing ISP (who was that again?)
<eiln_> something millenial
<marcan> millenialhacker, yes
<sven> millenialhacker
<marcan> they usually hang out in #asahi-re, maybe we should move ane talk there, seems like a decent enough place
<eiln_> oke
<sven> it kinda sounds like ane started as a fancy isp accelerator and then grew much larger :D
<marcan> since this isn't really GPU other than "probably will end up using the DRM/accel subsystem"
<marcan> sven: yeah lol
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<alyssa> Pass: 10413, Fail: 1653, Crash: 208, Skip: 6034, Timeout: 3, Flake: 5, Duration: 3:51, Remaining: 0
<alyssa> is it possible this number is going up >.>
<alyssa> (piglit)
<alyssa> i mean the # of passes is up but so is the # of fails
<alyssa> skip is basically the same
<alyssa> i guess piglit is weird and if you crash early entire tests just disappear
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