14:45 <sven> CIO3PLL_CFG_DCO_NCTRL.DCO_COARSEBIN_EFUSE0, CIO3PLL_CFG_DCO_NCTRL.DCO_COARSEBIN_EFUSE1, CIO3PLL_CFG_FRACN_CAN.DLL_CAL_START_CAPCODE_EFUSE, AUS_CMN_SHM_BLK_VREG_REG_0.VREG_TRIM, CIO3PLL_CFG_FRACN_CAN.DLL_CAL_START_CAPCODE_EFUSE, CIO3PLL_CFG_CLKOUT_DTC_VREG.DTC_VREG_ADJUST_EFUSE, AUSPLL_CFG_DCO_EFUSE_SPARE.RODCO_ENCAP_EFUSE,

14:45 <sven> AUSPLL_CFG_DCO_EFUSE_SPARE.RODCO_BIASADJ_EFUSE, AUSPLL_CFG_FRACN_CAN.DLL_CAL_START_CAPCODE_EFUSE, AUSPLL_CFG_CLKOUT_DTC_VREG.DTC_VREG_ADJUST_EFUSE

14:45 <sven> marcan: ^-- those are the fuses from xnu debug output for atc-phy1

14:46 <sven> even if that "PLL" wasn't in the same those very much sound like clock tunables

14:46 <sven> s/same/name/

14:56 <marcan> DLL is definitely a DLL, heh

14:56 <marcan> DTC_VREG though sounds like more of a physical layer thing

14:56 <marcan> not sure though

14:57 <marcan> could all be PLL tunables yeah

14:57 <sven> most weird one to me is AUS_CMN_SHM_BLK_VREG_REG_0.VREG_TRIM. dunno what CMN (common? not very helpful though) or SHM could be.

14:58 <marcan> SHM -> shim I bet

14:58 <marcan> CMN probably common yeah

14:58 <marcan> BLK -> bulk?

14:58 <marcan> or block

15:01 <marcan> also, wait

15:01 <marcan> AppleT8112TypeCPhy

15:01 <marcan> T8112?

15:01 <marcan> that has to be M2, right?

15:01 <sven> i guess so

15:02 <sven> there should also be T8103TypeCPhy and T6000TypeCPhy

15:02 <marcan> did they forget to censor that kext? lol

15:02 <marcan> yeah

15:02 <sven> lol

15:02 <sven> possibly :D

15:02 <marcan> T8110 is A15

15:03 <marcan> so yeah

15:03 <sven> chances are that one's similar to t6000/t8103 as well then

15:16 <marcan> https://twitter.com/nyan_satan/status/1407765762236952576

15:16 <marcan> apparently T6500 is a thing

15:17 <marcan> I'm betting that's a new Mac Pro chip

15:17 <marcan> everyone is assuming the Mac Pro will use 4x Max, and we know they're all wrong

15:17 <marcan> so it has to be a new chip, and that means it's either M2 Max or Pro

15:17 <marcan> but I'd expect M2 Max/Pro to use consecutive numbering like the T8xxx series did

15:17 <marcan> a big jump makes me think new line

15:36 <Dcow[m]> M1 BigMax

15:44 <_jannau_> assuming t6002 is jade 2c-die (M1 Max with interconnect) maybe jade 4c-die using a vastly different interconnect which supports PCIe x16 slots, external RAM (low bandwidth, high-latency but better and nvme swap)

15:50 <marcan> _jannau_: it wouldn't be jade, it's a new chip

15:50 <marcan> I think the jade 4c-die story is just BS

15:51 <marcan> that everyone keeps repeating

16:01 <marcan> reminder that that story came from Bloomberg, and we know how incompetent some of their tech reporters are ;)