ChanServ changed the topic of #asahi-re to: Asahi Linux: porting Linux to Apple Silicon macs | Hardware / boot process / firmware interface reverse engineering | WARNING: this channel (only) may contain binary reverse engineering discussion | RE policy: https://alx.sh/re (MANDATORY READ) | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-re
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<marcan> nicolas17: the order of the s-box entries is the bit order; the values are basically the indices, except skipping powers of two and some unused indices, and plus that parity bit thing
<marcan> I suspect there is no particular logic to the entry order, since it is truly arbitrary
<marcan> it does not matter at all, it's literally just the order of the wires in the circuit, and as long as the ECC computation is always consistent it does not matter
<marcan> same way the order of bits going into / out of an SRAM array does not matter as long as it's the same
<marcan> there's probably some underlying hardware reason for that order, but it might well be "someone hand-optimized the XORs" or "the synthesis engine optimized the physical layout"
<marcan> same with the skipped entries, it's also effectively arbitrary
<marcan> I saw someone comment that there's no way the s-box is encoded in hardware like that and there must be a simpler boolean reduction, but that's not true; it really is arbitrary and encoded in hardware like that because it literally is a mapping of XOR gates to the cache SRAM input bus
<marcan> the bus is probably 256 bits wide, as large as the sbox
<marcan> if it isn't and there is some folding into an e.g. 128-bit bus, there *may* be some higher-level structure, e.g. it can be split into two halves, but it depends
<marcan> but there may well not be too
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