<mareko>
another idea for primconvert is something like MinMaxCache, it caches min/max indices for vertex uploads so that it doesn't have to read back indices every draw
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<jekstrand>
anholt_: Wow. How on earth does that only affect XFB?
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<imirkin>
anyone know offhand how one does atomic ops on images in OpenCL?
<imirkin>
i see a read_image* and write_image*
<imirkin>
hrmph. doesn't seem like there is =/ there's atomic_fetch_key, but that's for simpler types
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<imirkin>
how would i go about retrieving the latest arm_test container (assuming i didn't want to mess with docker tooling)?
<imirkin>
(really i just want to grab some files out of it)
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<imirkin>
aha, got it. done -> lava-rootfs.tgz in the minio url
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<pq>
Was it documented somewhere how unportable the KMS CRC values are? As in, it never makes sense to save those and expect to get the same result at some other time, right? I couldn't find it in drm-kms.html at least.
<emersion>
i… didn't know that
<emersion>
is it really the case?
<emersion>
the CRCs won't necessarily be the same if you use two pieces of hw
<emersion>
but for a single display engine, i think they'll be stable?
<emersion>
i guess it _could_ depend on the firmware and stuff…
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<pq>
emersion, isn't the intended way to use CRCs to first render a single plane, get CRC1, then set up planes to achieve the same result, get CRC2, and compare?
<pq>
emersion, reason I started wondering in the first place is that I'd like to have VKMS CRC computation be not portable between CPU architectures.
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<pq>
for speed reasons
<emersion>
yes, the intended way to use CRC is to do that, because you don't want to have a database of expected CRCs for each hw combination
<pq>
right
<pq>
is that written down anywhere? :-)
<emersion>
i think CRC depending on CPU arch is completely fine
<emersion>
maybe in IGT docs? not sure
<emersion>
i don't even know if we have sysfs/debugfs docs
<emersion>
we do have some stuff near the kernel functions which send uevents iirc
<emersion>
> In this general case, the maximum userspace can do is to compare the reported CRCs of frames that should have the same contents.
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<pq>
that's a bit roundabout way to say it...
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<danvet>
javierm, btw how is the "dont load if another driver is registered" problem solved with simpledrm?
<danvet>
do we remove the simple framebuffer?
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<danvet>
javierm, ie. what's the equivalent for simpledrm of the patch I just r-b stamped?
<tzimmermann>
danvet, javierm, we have a config rule for either simpledrm or simplefb. maybe we should extend this to other generic fbdev drivers?
<danvet>
tzimmermann, oh that's another issue, but good point
<danvet>
tzimmermann, this was re [PATCH] fbdev: Prevent probing generic drivers if a FB is already registered
<danvet>
like what happens if you happen to load i915 first, and then you load simpledrm
<danvet>
will simpledrm still bind?
<javierm>
danvet: I was just looking that. We need to export a symbol to know if a drm device was already registered
<danvet>
javierm, feels a bit like a hack
<javierm>
danvet: I think that could be a wrapper around idr_is_empty()
<danvet>
javierm, I wonder whether we can't unregister the simple-framebuffer platform device
<danvet>
as part of "kick out firmware drivers"
<tzimmermann>
danvet, it will unfortunately. there was a bug report about it. but it's the same problem for genreic fbdev drivers
<danvet>
because once the real driver has taken over, the simple-framebuffer sysfb is very dead, and rather dangerous to use
<javierm>
danvet: that's a very good idea indeed
<danvet>
so just stopping loading isn't fully closing the gap
<danvet>
for fbdev we still need the hack, since these also load for other legacy platform devices
<danvet>
or I think sometimes without any underlying struct device
<danvet>
but for simpledrm I think we can model this neatly in the device model
<danvet>
javierm, if it works pls cc gregkh for review
<javierm>
danvet: yeah and even my patch is not nice because there's still race conditions. To make it safe we should take the lock used to register fbdev, but that would be a bigger change
<javierm>
danvet: sure, I will
<danvet>
javierm, looking in fbdev is fairly busted tbh, so *shrugs*
<javierm>
danvet: yeah, didn't think that would be worth it to make the refactoring to make it safe. And it's an improvement anyways over the current status quo
<javierm>
danvet: btw, do you want me to re-send with a Fixes: tag. Forgot to add it...
<danvet>
javierm, plus the second you drop the register lock someone might sneak in anyway
<danvet>
so wrapping locking doesn't fix anything
<javierm>
danvet: yeah, just make the critical section smaller
<danvet>
javierm, if you want, maybe wrap a READ_ONCE around them and add a comment
<danvet>
javierm, oh for that you can't because you'll get funny inversions
<tzimmermann>
danvet, native drivers should acquire their apertures, so that simpledrm can detect the conflict
<danvet>
I think the only way to close the race fully is to a) bind to platform device b) nuke said platform device when the real driver loads
<danvet>
tzimmermann, doesn't work well for anything that just uses ram I think
<tzimmermann>
danvet, that happens if generic drives are built-in and the rest is a module
<tzimmermann>
as it should be
<tzimmermann>
is there a way of controlling the order of device initalization?
<javierm>
tzimmermann: I was asking ardb yesterday if he thought that drivers/firmware should probably be earlier, before most subsystms
<javierm>
*subsystems
<javierm>
danvet: yeah, as said proably not worth it to attempt that since fbdev is (hopefully) going away soon anyways
<javierm>
danvet: but I'll send a v2 with a Fixes tag and a comment about why we make the probe fail. Thanks for your review!
<tzimmermann>
javierm, we'd need something right before device_initcall
<javierm>
tzimmermann: maybe simpledrm could be in subsys_initcall() ?
<tzimmermann>
dont know, sry
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<javierm>
tzimmermann: I see that's the case for drivers/gpu/drm/drm_dp_aux_bus.c for example
<javierm>
but on the other hand forcing specific init call levels is considered a hack and fragile...
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<karolherbst>
anybody here having some leftover space/time to hook up some nvidia jetson devices for mesa CI using nouveau? I sadly don't have the time to really build up a complete new CI system :/ And I was wondering if anybody here would be willing to hook up some devices here
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<alyssa>
dschuermann: any relevant papers about doing instruction dependency management
<alyssa>
(Like, when to insert wait instructions into a shader.)
<alyssa>
?
<alyssa>
If there's only a single slot you can wait on ("wait for every outstanding fetch to finish"), I guess it's easy
<alyssa>
But if there are N slots (mark each instruction as a slot 1...N and insert instructions waiting on a subset of slots) ... there's an optimization problem there I think
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<dschuermann>
memory or arbitrary?
<alyssa>
Technically arbitrary but practically just memory/texture loads
<alyssa>
for a sequence like "X = load(); Y = load(); Z = f(x); W = g(Y, Z)"
<alyssa>
pretending N = 1 is suboptimal
<alyssa>
since then you have to wait on both X and Y before computing Z
<alyssa>
whereas if you have 2 slots and can do "X = load(), slot 1; Y = load(), slot 2; wait slot 1; Z = f(X); wait slot 2; W = g(Y, Z)"
<dschuermann>
given that memory mostly returns in-order, I would just FIFO everything. how many slots do you have?
<alyssa>
then f can execute in parallel with the load of Y, which might be faster if f is super ALU-heavy
<alyssa>
6 and 3 for older and newer mali respectively
<dschuermann>
hm, that's not much
<alyssa>
FIFO is probably reasonably optimal locally, but might perform weirdly globally
<alyssa>
🤷
<dschuermann>
AMD has a counter and we see it going up to ~14 quite often
<alyssa>
Hm, okay
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<alyssa>
I recalled ACO has to do something with wait insertion but don't know the details, so thought I'd ping you in case this is a solved problem for you :)
<dschuermann>
so, you'd have to wait for a slot to make it available again, or you'd push another memory instruction to it, and have to wait for the latter when the first is being used
<alyssa>
right, that's our problem too
<alyssa>
N = infinity is functionally the same as N = 1 😋
<dschuermann>
what I'd try: if you run out of slots, push everything to the last outstanding one, so that these get bundled together, but the others don't get clobbered. they'll free up, and you can re-use them
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<alyssa>
"outstanding"?
<dschuermann>
example: X=load slot0, Y=load slot1, Z=load slot2 (out of slots here), A = load slot2 (the last being waited on), B = load slot2... wait slot0, use X, C = load slot0 (was free again, and can be reused), D = load slot0 (last being waited on), etc...
<dschuermann>
that is not optimal, but should be a good start
<alyssa>
Ah, sure
<alyssa>
Yeah, that seems reasonable as a first start indeed.
<alyssa>
I suppose I shouldn't overengineer this, currently I am waiting for everything always and literally anything is better than that 😅
<alyssa>
("Enough threads will hide the latency, right? Right?")
<dschuermann>
another idea would be to combine loads from the same descriptor / address, but different offsets
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<dschuermann>
Enough threads will trash your cache, eventually ;)
<alyssa>
heh
<dschuermann>
the same-descriptor thing, I'd only do on back-to-back loads
<alyssa>
Sure
<alyssa>
so these are ACO problems too, or..?
<imirkin>
what's the format for deqp-runner skips? is it PCRE or glob?
<imirkin>
i.e. ".*" or "*"?
<alyssa>
imirkin: I think glob?
<alyssa>
PCRE seems excessive anyway
<imirkin>
agreed, but it's whatever's implemented. and it's in rust, which i'm unfamiliar with, so hard to track down myself
<dschuermann>
for vector loads, these are in-order and we just have a counter. for scalar loads, these can return out-of-order and we always have to wait for everything. we don't optimize this case (yet), like waiting before another load to avoid stalling when the first is being used
<alyssa>
dschuermann: got it
<alyssa>
the vector vs scalar load distrinction is an AMDism I guess?
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<alyssa>
imirkin: Apparently I'm wrong and it is regex after all
<dschuermann>
yes, AMD has a separate scalar register file, ALU and scalar load/store unit for subgroup-uniform values
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<clever>
mripard: ive been experimenting with the rpi lately, and ive found that SCALER_CTL0_SCL_H_TPZ_V_NONE is unreliable on a pi3, sometimes it works, and then it just goes nuts and stops working right
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<clever>
mripard: the current linux source will disable scaling when src/dst match, but ive found that the closed firmware uses TPZ with a 1x scale a lot of the time, and SCALER_CTL0_SCL_H_TPZ_V_TPZ did solve my issues
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<mareko>
more threads can thrash your cache; sometimes inreasing (even doubling) the register usage and scheduling for better cache hits and latency can deliver better performance
<jekstrand>
jenatali: Wouldn't that mean you have two different implementations of the same thing?
<jenatali>
jekstrand: No. The loop comes around, finds the main function, fills out that entry. Then iterates again, finds the same disp_index for the alias, and the function in the dispatch table isn't null
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<jenatali>
Guess it could be disp[disp_index] == NULL || disp[disp_index] == entry[i]?
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<jenatali>
Oh, wait, no I see what my problem is. Incremental linking breaks the not-implemented logic
<jekstrand>
jenatali: I guess if you filled out bout entrypoints to point to the same thing
<jenatali>
Awesome
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<jekstrand>
Incremental linking?
<jenatali>
Yeah. It breaks the /alternatename thing
<jekstrand>
*sigh*
<jekstrand>
I hate the weak function pointer stuff
<jekstrand>
It's just so dang useful
<jenatali>
Since it gives each /alternatename function a different address, to a single-instruction jump to the actual stub
<jenatali>
It's too magic IMO. Too hard to diagnose when it's right vs wrong. A typo may cause a silent runtime error instead of a compiler/linker error
<jekstrand>
yeah
<jekstrand>
I just hate the alternatives
<jekstrand>
I'd be happy to have some counter-proposals.
<jenatali>
Yeah I don't necessarily have something better, I just know I don't like this :)
<jekstrand>
Then we're agreed!
<jenatali>
Yeah, turning off incremental linking explicitly fixes my debug build
<jenatali>
That probably needs to be documented somewhere as an MSVC quirk for the VK entrypoint stuff...
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<jekstrand>
dj-death: Rebased the common sync branch on your change and kicked to Jenkins again