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<robclark> rather not block shrinker (ie. not at least until you know there isn't lower hanging fruit in the system).. otoh at some point it becomes worthwhile to block, if you are calling shrinker as a result of trying to pin yet more bo's for queing the n+1'th submit/execbuf. I guess in some sense it would be useful to know whether we are in shrinker as result of our own memory allocation (in which case blocking==good) vs someone
<robclark> ickle: btw, have you considered using whether shrink_control::gfp_mask has GFP_NOWAIT bit set as a signal that it is worth it for shrinker to block on active bo's to become idle? i915 doesn't seem to do that but I'm kinda thinking about it re: igt gem_shrinker tangent I mentioned in <CAJs_Fx6Nc337LPNh=p2GT2d2yDTdLWH934o4Cof3urDGhUJB6A@mail.gmail.com>.. one one hand, in early stages of memory pressure you probably would really
<robclark> else's..
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<mi6x3m> hey, i need some info as to what is going on. I start something with MESA_LOADER_DRIVER_OVERRIDE=swrast then i get this output https://pastebin.com/mSMSQ9jG but LLVM is used normally
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<mlankhorst> demarchi: Sorry, haven't done much gem work much lately, I'd inspect which fence is being installed I guess
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<pepp> would anyone want to give https://gitlab.freedesktop.org/mesa/piglit/-/merge_requests/680 a second look? (context: adjacency primitives + provoking vertex)
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<emersion> vsyrjala: HDMI content type question: is this accurate wrt the "graphics" type? https://gitlab.freedesktop.org/wayland/wayland-protocols/-/merge_requests/150#note_1397638
<emersion> also what does the driver do when user-space uses "no data"?
<emersion> i suppose it doesn't set the IT flag?
<emersion> it sounds to me like it would be better for compositor to unconditionally set the content type to "graphics" by default, when a more precise type isn't available
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<krh> do we have minimum python3 version in mesa?
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<demarchi> mlankhorst: yeah... talked to Nirmoy after that message... we are indeed passing an array. He's working on a patch to fix that
<demarchi> mlankhorst: thanks
<enunes> hi all, could someone take a look at my gallium / st changes in https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16136 ?
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<jekstrand> pepp: Do you have time to test !4037 and make sure custom-queue blits still work?
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<pepp> jekstrand: I'll try tomorrow (today's attempts failed because my built kernel wouldn't boot)
<jekstrand> pepp: Ok, thanks! As long as you're moving them forward, the kernel patches should be pretty easy to rebase. But they are based on big rework from Christian König at AMD so you can't port it back very far.
<vsyrjala> emersion: i think the behaviour in the itc==0 case is undefined. but maybe someone likes what it does on their specific display, so i'd be a little hesitant to not inclue it in the protocol
<emersion> vsyrjala: that makes sense. but do you think setting "graphics" by default would be a good behavior for compositors?
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<vsyrjala> yeah, sounds like a reasonable default for ui stuff. wonder if we should even make that the default in the kernel...
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<emersion> that would be nice
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<zmike> jekstrand: are you the person to look at https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16619
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<jekstrand> probably?
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<alyssa> ..I should probably wire up nir_opt_large_constants...
<alyssa> I guess the load_constant -> load_ubo lowering isn't common, though
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<jekstrand> alyssa: No, that's per-driver. In the Gen8+ Intel drivers, we actually stick the constant blob at the end of the shader binary, bake the address into the shader, and use nir_load_global for it.
<jekstrand> No UBO binding required. :)
<HdkR> Sounds like a good reason to have a PC relative load in your GPU ISA :D
<alyssa> jekstrand: Heh, it's an option!
<alyssa> HdkR: Bifrost has it but I refuse to wire it uP ;p
<alyssa> Valhall doesn't, AFAIK
<HdkR> boo
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<jekstrand> On Intel, we have nir_intrinsic_load_reloc_const_intel
* alyssa wonders what the fastest way to do it on AGX is
<jekstrand> It emits a MOV dst <IMM> but with some extra metadata in brw_stage_prog_data telling us where it lives in the compiled binary so we can patch the actual immediate value later. Then we do the patching right before we upload it.
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<alyssa> Pretty cursed tbh
<jekstrand> It is a bit cursed, yes, but it's also pretty awesome.
<alyssa> Heh
<alyssa> I wonder if we could make that work ...
<jekstrand> How easy it is depends on your instruction encoding. On Intel, we can ensure that the immediate is a 32-bit thing that's nicely aligned.
<alyssa> Mm
<alyssa> Sounds pretty impossible on Bifrost for example
<jekstrand> IIRC, it requires us to initially emit it with a constant value that we know will cause instruction compaction to give up.
<alyssa> Cursed
<jekstrand> Cursed but useful
<alyssa> There's no obvious 'best' way on Valhall
<alyssa> WTH
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<graphitemaster> I reading the entire email thread started last year about moving from implicit sync to explicit sync everywhere during my vacation because of a phronix article - that whole thing needs a summary, but also is there any updates on that project, like a newer thread, I'd like to follow it.
<bnieuwenhuizen> graphitemaster: which one?
<graphitemaster> Was quite a journey reading through all of those, but it seems the conversation went cold
<bnieuwenhuizen> no idea about that part of the puzzle
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<graphitemaster> The gist of it seems to be that everyone wants to do explicit sync but it's a nightmare making it all work with the existing drm sync primitives and wsi / compositors
<graphitemaster> But having explicit sync would effectively solve most of the userspace stability issues when it comes to preemption
<graphitemaster> And make timeline semaphores in Vulkan actually work the way they're supposed to work
<bnieuwenhuizen> explicit vs. implicit sync and preemption are kinda orthogonal actually
<graphitemaster> Well it has to do with the whole deadlock/timeout scenario specifically, letting user-space spin on something every frame rather than tearing shit down works much better from a robustness standpoint when it comes to long running compute kernels
<bnieuwenhuizen> the problem is that dma_fence (whether it be explicit or implicit) has semantics which are too strong due to being a blocker for memory stuff
<graphitemaster> right, there was a suggestion of drawing some artificial lines between dma_fence use at the wsi layer and non-wsi layer where distinctions can be made and encoded so weaken the semantics of it where it's necessary
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<graphitemaster> I really liked that suggestion.
<graphitemaster> Rather than adding yet another sync type
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<graphitemaster> Move more of the work into the compositor mainly when it comes to unresponsive stuff too, that feels very appropriate to me. Less in kernel space the better, the more applications using APIs like Vulkan where the whole robustness argument is moot and can just hammer frames without anyone in their way the better I think as well.
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<graphitemaster> Let the compositor just render garbage when tearing down an incomplete swap
<graphitemaster> It'll eventually be repainted
<graphitemaster> Lots of really neat suggestions in there.
<graphitemaster> I'd be curious what Windows does
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