<tarceri>
I'd like to push right away so I can start a MR that updates the piglit version in CI
<zmike>
acked
<tarceri>
Thanks!
<zmike>
👍
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<MrCooper>
ugh, ckoenig forgot to Cc dri-devel on his "Per file OOM badness" series
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<jekstrand>
danvet, bnieuwenhuizen, dj-death, emersion: Where are we at on dma-buf sync_file import/export?
<jekstrand>
I reviewed emersion's patch for the caps dir and updated the Mesa MR to use it. It'd be good to get ACK/RBs on the FIXUP patch before we call everything good-to-go, I think.
<jekstrand>
Also, if someone who knows something about distros/containers for realz wanted to comment on sysfs, I'd be open to it.
<jekstrand>
I'd really like to be able to rely on it but maybe sysfs isn't available sometimes for good reason?
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<jekstrand>
If we ever hit that, we can detect the ioctl via other means. They're just really annoying if we want to do it up-front from nothing but a VkPhysicalDevice. (Basically, create a VkDevice, allocate some memory, try, throw everything away.)
<bnieuwenhuizen>
jekstrand: which patch are you going to move the FIXUP patch into?
<jekstrand>
Top one, I think.
<jekstrand>
"vulkan/wsi: Signal semaphores and fences from the dma-buf"
<jekstrand>
Here, let me add a printf warning if we ever can't find sysfs.
<dj-death>
jekstrand: I rb it, feel free to smash it to another commit
<emersion>
i need to make sense of what greg replied
<emersion>
i'm a little bit lost i must admit
<jekstrand>
emersion: Oh, I didn't see greg's reply
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<jekstrand>
emersion: Did Greg's e-mail not make it to a list? I don't have it anywhere AFAICT
<jekstrand>
emersion: If you fwd, I can try to help you sort through it.
<emersion>
you were copied, and so was the list, lemme give a link…
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<jekstrand>
Wait, what?!? Why is my depth value ending up in my stencil buffer?
<jekstrand>
Oh, because it's 1.0 / 255
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<jekstrand>
Looks like maybe stencil is messed up somehow?
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<jekstrand>
Hrm... This test uses secondaries. Maybe those are busted?
<alyssa>
anholt: " glsl,nir: Move i/umulExtended lowering to NIR." is some kind of magic debugger, I think
<alyssa>
we're up to 5 distinct bugs in the Midgard stack it's uncovered
<alyssa>
kudos, really ...
<jekstrand>
alyssa: :)
<jekstrand>
alyssa: It's required for CL anyway, so...
<alyssa>
jekstrand: Midgard OpenCL is a NAK from me, unless icecream95 does that RiiR of the compiler he keeps threatening :-p
<alyssa>
this codebase is just so fundamentally broken
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<Gambino>
Ily CL
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<jekstrand>
I was doing secondaries wrong but I fixed them and they're still broke. :'(
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<anholt>
enunes: why do you need a new cap? you should be able to just set that you support either orientation in the existing caps
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<enunes>
anholt: I looked for a bit and couldn't identify any cap to reuse. But I'd be happy to not add it if there is another way
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<anholt>
enunes: set both upper left and lower left caps
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<enunes>
anholt: we do have both set right now, but the nir pass still adds some code anyway
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<enunes>
I didn't look too much into the details of it to see if it is a bug in the pass
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<anholt>
I think if there is any change to be done, it should be within the pass and with no new caps or state.
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<anholt>
Maybe need a variant at the st level for turning FlipY (GL_MESA_framebuffer_flip_y) into shader_info state instead of relying on the wpos transform
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<enunes>
ok I'll take another look at that. Thanks
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<jekstrand>
emersion: Does gregkh's latest e-mail make more sense?
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<alyssa>
Venemo: For AGX, I need to lower away vertex inputs to load_global
<alyssa>
Currently I'm handling this in the backend when translating load_input
<alyssa>
(using the backend IR builder with the shader key and piles of implicit sysvals)
<Venemo>
alyssa: sounds similar to what we're doing with our I/O
<alyssa>
Yeah.. was going to ask, any code that we could share if moving that to NIR?
<alyssa>
(Ditto for lowering away UBOs to load_global_constant)
<Venemo>
hm good question
<alyssa>
The ACO stuff looks very AMD-specific which suggests no but shrug
<alyssa>
Admittedly the AGX stuff is pretty AGX specific too in parts
<alyssa>
In particular, AGX has formatted load/store instructions
<alyssa>
e.g. "load 4 bytes from this address, interpret it as rg11b10f, unpack, and store 16-bit floats to consecutive registers"
<Venemo>
alyssa: the VS input lowering is not finished yet, it currently handles 2 out of 3 possible code paths. there is the possibility to load from a dynamic VS input (meaning, from a register that the prolog shader prepares), there is a version that can use untyped buffer loads, and finally one that has typed buffer loads. this last one is not included yet.
<alyssa>
I don't know how well we can model that in in NIR
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<alyssa>
"typed buffer loads" is a good name I suppose :)
<Venemo>
alyssa: now, for the dynamic inputs, those I could shove under a different rug, but for the other two, the good question is can we abstract away the hw specific pieces without making the code suboptimal
<alyssa>
right
<alyssa>
You can imagine how formatted (typed?) loads make a big difference for code quality for AGX
<Venemo>
amd calls it that, hence why I use that term
<alyssa>
ack
<Venemo>
if you look at store_buffer_amd/load_buffer_amd in nir_intrinsics.py, basically that is what both of them look like. the "typed" ones also have a format field in addition.
<alyssa>
Likewise there's an integer multiply-add instruction which means the common "stride * gl_VertexID + offset" addressing is one instruction
<Venemo>
alyssa: also, if you like shader I/O you can check out how we handle it for other stages in amd/common/ac_nir_lower_xxx_io_
<alyssa>
Though probably we just want imad in NIR and an algebraic opt since IIRC that's a pretty common instruction
<alyssa>
ack
<Venemo>
if you have a good idea how to handle this in NIR in a less HW dependent way, we can share some code for sure
<Venemo>
it's not a lot of code though, so dunno how much it is worth the headache of sharing it
<alyssa>
Yeah, I feel that
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<Venemo>
I do recommend handling this sort of thing in NIR, though, it is just so much more flexible than whatever we can do in the backend
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<alyssa>
yeah...
<Venemo>
for this vs input lowering thing, honestly I'm not even sure yet if this makes sense for radeonsi, otherwise I would've put it in ac_nir_ like the others
<Venemo>
alyssa: what does the AGX instruction do? the AMD one definitely can do a lot of things at the same time
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<anholt>
alyssa: mark imulextended as skip, not xfails?
<alyssa>
anholt: xfails works too
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<anholt>
alyssa: does your ack cover the "scalarize for doubles" change?
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<alyssa>
anholt: yes
<anholt>
thanks!
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<alyssa>
Does Vulkan allow multiple simultaneous occlusion queries?
<anholt>
I can imagine useful lowering passes done in the GS, so it's not concerning to me but might be strictly incorrect.
<jekstrand>
oof
<idr>
jekstrand: I would guess that the implementation @may use relaxed precision on a per-operation basis, but doing so can violate the principle of least surprise. :(
<jekstrand>
idr: Pretty sure mediump operates on the principle of most surprise. :P
<idr>
I think I want "mediump operates on the principle of most surprise" on a t-shirt for the next Khronos f2f.
<alyssa>
Lol
<daniels>
idr: *mdup oeae o te picpe o ms srrs
<idr>
Heh...
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<anholt>
daniels: did you get your rounding right in your conversions there?
<alyssa>
anholt: sms fne t me
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<daniels>
anholt: implementation-defined; this one uses upside-down-endian
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<icecream95>
alyssa: Okay okay I'll rewrite the Midgard compiler if you want me to
<icecream95>
But only if you fix all the G31 bugs in return...
<alyssa>
Ooh, that's a tough one...
<alyssa>
I don't think I've booted my G31 since August when I learned the CTS no longer works without 4GB of RAM
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<icecream95>
Could you reduce the maximum texture size for G31 then?
<alyssa>
The iffy party was deqp-gles31.indirect.large_interop or something
<alyssa>
There was a CTS bug that was never fixed for it because everybody who complained just upgraded their test boards to something with more RAM ....
<icecream95>
So then why couldn't you skip those tests?