ChanServ changed the topic of #dri-devel to: <ajax> nothing involved with X should ever be unable to find a bar
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<zmike>
I hope it blends
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<ILOVEPIE>
Can someone point me to where i can find information on the nir_intrinsic_first_invocation instruction? I noticed it was missing from the nouveau compiler and it's causing issues with running a specific piece of software through NVK, I wanted to try my hand at fixing that since it seems to be a rather simple instruction.
<alyssa>
nir_intrinsics.py
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<karolherbst>
it's kinda cursed, but maybe you have better ideas?
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<karolherbst>
but would also be helpful to get input from others, because that feature is really cursed...
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<jenatali>
karolherbst: I'll take a look
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<karolherbst>
jenatali: I wonder if it makes sense to implement this for real from the start, but that's really annoying to do actually... my current plan is to have an entirely new entry point to vtn with a custom vtn_handle_constant which just emits it into a init entry point....
<karolherbst>
and have some nir opts which can optimize stores to the global var to a value in the initializer.. but that's even more work :')
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<jenatali>
karolherbst: I'm traveling today so if I don't take a look by end of week, tag me in the MR so I get an email I can use as a reminder
<karolherbst>
okay, have fun!
<jenatali>
These IRC pings come in at 4am and by the time I'm actually in front of a PC I sometimes have forgotten :)
<karolherbst>
heh
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<Hazematman>
Hey I've had this MR sitting for a little while right now to enable dma buf import & export support in llvmpipe & lavapipe. I was hoping I could get some feedback on it and get it landed https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27805
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<zmike>
I'm getting to it
<zmike>
it's been a busy week
<mareko>
robclark: I'd like it to have a better comment after return is_drm_shim;
<mareko>
zmike: I think you need to re-run divergence analysis because nir_opt_varyings sets it to vertex divergence
<demarchi>
related to the move of (most) repos to gitlab
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<mripard>
demarchi: done :)
<zmike>
mareko: yeah that seems to fix things, thanks again
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<robclark>
mareko: newer version just marks userspace fences signaled after submit.. but still OoM's mid way thru drawoverhead, so I guess I'm missing something
<alyssa>
jenatali: how do samplers in descriptor sets work in dozen?
<alyssa>
given that dx12 has a limit of 2048 samplers in the heap, but vk allows creating 4000 samplers?
<alyssa>
particular with EDI/update-after-bind
<jenatali>
alyssa: we bumped the limit due to that VK requirement
<alyssa>
how can that work? wasn't the limit already tight on nvidia?
<jenatali>
The 2048 limit comes from NV. They have 4096 max, which we partition into 2048 app samplers, 2032 static samplers across all possible root signatures (like descriptor set layouts), and 16 driver-reserved
<jenatali>
To get 4k you have to give up on the static samplers, which aren't beneficial for them from a perf POV anyway, just developer convenience
<alyssa>
(and does this cause a problem in turn where vk needs to bump limits for vkd3d-proton, and then we just end up in a layering feedback loop until both vk and d3d12 require infinite samplers?)
<alyssa>
:P
<DemiMarie>
🤣
<DemiMarie>
Has anyone actually tried VK on D3D12 on VK on D3D12?
<DemiMarie>
I guess a Vulkan app running under Wine would be VK on D3D12 on VK.
<karolherbst>
nah, they just do vulkan directly for most part
<jenatali>
Why? It'd just be vk
<DemiMarie>
I thought Windows didn’t guarantee that Vulkan was present, so one must bring one’s own VK-on-D3D12 implementation.
<mareko>
zmike: divergence information currently is not guaranteed to be correct or up-to-date anyway if you have run any passes after divergence analysis, so any pass that uses "divergent" should have it re-run
<zmike>
got it
<zmike>
makes sense
<mareko>
Daniel suggested making it metadata that a pass can "require"
<karolherbst>
DemiMarie: why would that matter for windows?
<karolherbst>
*wine
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<DemiMarie>
karolherbst: I wasn’t sure if there was a way to check if the driver used Vulkan
<DemiMarie>
*supported
<jenatali>
Demi: apps can and do assume it's present
<jenatali>
Dozen exists partly for that reason, so we can provide a fallback for the case where the driver doesn't provide it
<jenatali>
alyssa: I don't think that'll cause problems for vkd3d. But does that answer your question?
<glehmann>
they are beneficial for AMD perf
<glehmann>
> To get 4k you have to give up on the static samplers, which aren't beneficial for them from a perf POV anyway
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<jenatali>
glehmann: right, I meant specifically for NV
<jenatali>
The way we lifted to 4k is for drivers to specify a separate limit for static samplers
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<alyssa>
jenatali: mind linking relevant dx12 spec? not having luck searching
<jenatali>
Note that we only have this problem for update-after-bind descriptors. We have a path which copies descriptors at draw time which has no limit on the number of samplers alive at a time, just per pipeline layout
<jenatali>
But we can only use that path if we don't enable the descriptor indexing extension
<alyssa>
yep
<alyssa>
jenatali: tangentially related -- does dx12 spec a limit for static samplers accessed in a single shader?
<jenatali>
alyssa: no, 2032 total alive at a time though
<sima>
jfalempe, yeah macro sounds like a good idea if that helps
<sima>
and best to match semantics of the spinlock functions as close as possible
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<canonjet>
dwfreed, so you look at the onion server or tor service exit node, and freeze my socket which would freeze any of the gui functionality to initiate new widget through the main oftc connection, it actually has visible side effects on all clients. but you could do it more intelligent i assume that i would not understand i am cut off.
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<tomeu>
so, I have my userspace driver for the rockchip NPU already doing useful stuff, but the UABI header for their (out of tree) kernel driver is GPLv2 only
<tomeu>
how much of a problem is that to get the code merged into Mesa?
<alyssa>
tomeu: a lot, afaik
<alyssa>
this is part of why no kbase in mesa
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<tomeu>
yeah, I vaguely remembered that being a problem
<tomeu>
alyssa: that said, won't you happen to have a commit laying around with an empty skeleton of a DRM driver? maybe from asahi?
<alyssa>
I pretend that I've never done kernel work
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<robclark>
alyssa, tomeu: tu _does_ have support for downstream kgsl uapi... although, it isn't, like, the primary uabi, just an alternative so one can tu on android vendor kernels
<alyssa>
robclark: but the kgsl uabi headers aren't gpl..?
<robclark>
we do have uabi headers for a bunch of kernel drivers which are gpl, incl panfrost
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<alyssa>
robclark: the uabi headers are specifically not gpl, unlike the driver
<alyssa>
(although panfrost was relicensed as mit recently)
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<alyssa>
Linux-syscall-note
<alyssa>
though if kbase & rknpu have that I guess it's ok
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<robclark>
looks like the syscall note is not specifically called out for a bunch for drm-uapi.. but I guess it is implied in that they are kernel uabi.. possibly some of that should be fixed on kernel side and sync'd back to mesa (ianal)
<alyssa>
wheeeee.
<tomeu>
this out-of-tree driver is plain gplv2... :(
<DavidHeidelberg>
maybe the header isn't copyrightable?
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<DavidHeidelberg>
License is usually everywhere, but that doesn't imply it's really applicable everytime it's present
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<gfxstrand>
I'm not intending for it to be an exact, detailed description of how control-flow works, just a hand-wavy description that's good enough for reasoning about re-convergence for the sake of a blog post.
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<robclark>
gfxstrand: maybe of note, on qc we need to mark potential recovergence points
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<gfxstrand>
robclark: Yes but getting re-convergence right is based on high IPs, right?
<cwabbott>
yeah, it's the same as ARM - the lowest IP is always the one executing and parked invocations have higher IPs
<cwabbott>
and also just like ARM you need to mark points where active threads fall through into parked threads
<cwabbott>
it's implemented as a priority queue of (inactive IP, inactive thread mask) instead of a simple vector IP, which we unfortunately have to care about in the compiler because we have to program a register with the max size, but that's too much detail for a blog post
<alyssa>
gfxstrand: ack for apple & arm
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<cwabbott>
gfxstrand: there's also a fun corner case where NIR's block ordering doesn't work, for continues
<cwabbott>
that's a case where always having continue constructs all the time would be helpful
<cwabbott>
I have to manually create one in ir3, and panfrost is probably just broken
<alyssa>
can confirm
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<gfxstrand>
cwabbott: Right
<gfxstrand>
cwabbott: We could have a pass that just adds empty continue constructs everywhere.
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<kiarash>
hi
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<karolherbst>
jenatali: btw, I'll just do the initializer lowering to init kernel code right away.. it's just a lot of work, so I guess you won't have to look at the MR for a while
<DemiMarie>
gfxstrand: wow, I was not expecting GPU ISAs to be that weird!
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<gfxstrand>
Oh yeah, they get funky
<mareko>
is AMD the only not having a weird ISA for once?
<Sachiel>
there's nothing weird about the Intel ISA
<Sachiel>
except for all the weird bits
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<karolherbst>
I hate this feature...
<gfxstrand>
mareko: I think AMD GCN and NVIDIA Volta+ both make sense in their own way and everything else is some weird eldritch horror in between the tow.
<gfxstrand>
*two
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<DemiMarie>
gfxstrand: which one is closer to what the actual execution units see?
<DemiMarie>
in other words, which requires the least control logic?
<zmike>
eric_engestrom: I'm not sure anyone has said this recently, but I have to say it
<zmike>
thanks.
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