ChanServ changed the topic of #dri-devel to: <ajax> nothing involved with X should ever be unable to find a bar
<zmike>
uhhh
<zmike>
never seen that before
<zmike>
hmmm I think I can imagine how it might happen
<zmike>
too bad I'm at the pub
<karolherbst>
have fun, but also, why are you checking in on IRC while in the pub
<Ristovski>
one does not waste optimization opportunities, no matter the occasion
<zmike>
I got a ping, I checked the ping
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<treasureXsafe>
the war is somewhat wished to be seen to kill the wank spammers and those whore sluts that give anal to penniless crank gangsta buffalos, you wasted all my vacation you retarded human shit. One gang sold catgold another was "buying" our hotel other anal buffalos were harassing all the tourists with their schizophrenia talks from aussie to estonian to south-african to nigerian lamplegs
<treasureXsafe>
kill off's are delegated to chinese in that region.
<treasureXsafe>
along with their whores i'd be happy to use firearms to gun them to a ghost filter, the duo of bi's is still harassing our clients there, and to be exact, i never communicate with this human excrements, neither is anymore any clients from the rest of the world coming, the hotel is bought from my assets, but i do not care enough to go there either to environment which is human shit. The
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<cheakymister>
for quantum technologies there used to be 15 or more different approaches, and with those chips that land on some other planet to compute, not very much known to me as to what they gotta do to keep them running in X conditions but i do not think there is a problem to pack as much data as needed to get the gas fuel rocket to start okay. so what was not registered was there is a web blog
<cheakymister>
where a guy made quadruple precision that of n length registers, which ends up as intrinsics for plus and minus instructions, one guy had those on the net quite long time ago already, as i am saying technically quantum computers experimental are not quicker than usual classic computers, i'd expect fpgas to hoise more horsepower. But i can not really dig out any words of relevance
<cheakymister>
anymore, it has been for some time for me, a real time to go mind my own business.
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<randomgigolo>
same intrinsics would work on decoder encoder and all the operations in compressed formats too, but i tend to think the most powerful execution format is double compressed, those intrinsics i talked about a few but there might had been some mistakes i did, i do not recall or remember the logs but such intrinsics might be more the less to taclke lattice based cryptography i would assume,
<randomgigolo>
however i have not delt with that type of cryptography. double compressed intrinsics would solve tremendous amounts of alus more than 300qubits. You have such intrinsics working that means a danger, but i had done some brainhurting on those already, and i know its possible. again only minus plus needed. To be honest cambodia was in a state of such criminal gangs floating around, that
<randomgigolo>
were quite as not only obnoxious only with their anal sluts, but they were dangerous to tourists, thieves as well as cold hearted murderers what you would expect from syndicate gangs anyways right, who only talk about their mob stories, during such moments the military has to take over there. I ignored those gangstas and delt with my own research so science i chose.
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<clashoftitaneggs>
https://www.youtube.com/watch?v=-UrdExQW0cs 20million qubits is out of reach however classical computers can do it with less. double compression would give one alu unit in 20cycles 300qubits, this is basing on calculation that 64qubits divided by 65336 is now stuffed so, that every after 65536digits you have 64qubits, and 64bits register can have trillions of them. so every 2 then 4
<clashoftitaneggs>
then 8 is two times more than in the beginning per bank , roughly that brings one hundreds of qubits, but rdna3 or such card has tremendous amounts of simds of 64bit width, and i do not think more than two times the it can be packed, so wild guess would be 100rdna3 cards to break rsa encryption i think rdna 3 had 2048 simds. so on 2048 simds we are on roughly 2000qubits, then on
<clashoftitaneggs>
20000 with 10 and 20million on 100 of such, those are likely very broken calculations but point is the time is already there.
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<tenorgifsuedme>
considering that i offered this without any chatgpt usage i got it pretty close probably since trillion times trillion is septillion, that google answers is 10 in power of 100, so 300qubits is 10 in power of 90 which so double compressed format has above 300qubits indeed, now the cards are different some might have 32768 compute units these days i'd assume, but this goes already over
<tenorgifsuedme>
my budget. however there are further tricks possible so i tend to belive not only that rsa1024-2048 is already broken many times by hackers, maybe it's achievable with only 10graphics cards rather but whatever.
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<pistolsmoke>
maybe someone wants to meet those estonian fuck aces that spam the world with wankterror , da real deal instead of my techtalks. Asses full of biritish scumbags load. Terrible people. still i think encoding banks outside the hash itself that goes into one register, no longer makes sense, there are zero delay interrupts possible yet, and mixture with non-compressed intrinsical methods,
<pistolsmoke>
however more than that i do not see getting done, i do not think i am capably in form for this, nested compressed intrinsics would give entire maniac results, but one needs to come out with some addressing schematic, i have not landed to that spot with any of my thoughts. Nested ones are probably possible but that has already complexity, i am not prepared for this and i exhibit no form at
<pistolsmoke>
all tbh. in mathematics or programming, it's just what i talked about is very simple schools material before.
<jenatali>
zmike: Yep, fixed it
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<zmike>
jenatali: cool
<zmike>
does it work for whatever you were testing too?
<jenatali>
It exhibits the same bug I was seeing with the d3d12 backend and softpipe
<jenatali>
I.e. not my bug :)
<zmike>
cool
<zmike>
wait softpipe?
<zmike>
or llvmpipe
<jenatali>
Softpipe. This is an arm64 laptop and I didn't feel like building llvm
<nosmokefrom>
they do not really specify what is the background of that measure of 20million qubits, what's the rsa breaking algorithm in mind, if that never takes use of any addressing redecoding and encoding like shown on the clip so factor to until 1 and add the fourier transform and append exponents, got sakes i would tell than that nested compressed intrinsics would break rsa with single computer.
<nosmokefrom>
Since you do understand when you readdress the results of the intrinsic and re-add and re-subtract those results, the computation efficiency polynomialy grows. when you add one septillion to another septillion guess what happens etc. it would resolve indeed now this number of alus. But my brain started to hurt, and this dwfreed is killing me, guy needs another coffin to be tailored to
<nosmokefrom>
him, we make on for jack already. Terrible people, seems airlied coworks with estonian wank spam ass hero real deal shitfaces, pardon i do not like to get involved with any stalkharassing me over their "private" achivements, it's definitely very tactical as well as advanced to get between the fart from illman from england but it looks like they do not stop their spam and abuse to the not
<nosmokefrom>
interested people like me, so we are even i would want to kill you as much as you would me, and we'll see who succeeds, however only abusers were you, i already did my time 2years in mental insitution and in estonia that is lot stinkier and dangerous than jail. And that is your favours to me youo fucking scum.
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<alyssa>
how is host_image_copy supposed to work with sparse? o_O
<zmike>
it's not
<alyssa>
then why is there CTS for it :clown:
<zmike>
or maybe it is and I misremembered
* alyssa
returns not_supported and CTS shuts up
<alyssa>
deeply unserious
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<zmike>
smh how will anyone use this driver
<alyssa>
holding it wrong
* HdkR
aims graphics driver directly at foot
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<jenatali>
... how do you do sparse with host access at all?
<zmike>
very carefully
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<alyssa>
jenatali: that is my question
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<alyssa>
I guess lavapipe could do it
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<memleak>
hello, i've been working with X for many years and trying to help a guy out with a really obscure problem and i'm stuck.
<memleak>
he's using an intel board with a i915 GPU that is too new for the 5.4 LTS kernel so I helped get his system to use fbdev first with simplefb, that didn't work (no suitable framebuffer found) even though /dev/fb0 was there
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<memleak>
next i tried to get vesa going for him by uninstalling the xorg xserver fbdev driver to help shut vesa up, but now he gets: V_BIOS address 0x0 out of range
<memleak>
vesa doesn't want to start if fbdev is available and if /dev/fb0 is present so i satisfied those dependencies for him
<memleak>
never in my life saw this V_BIOS address 0x0 out of range problem before and no idea how to fix.
<Ermine>
is upgrading to newer kernel an option? There are newer LTS kernels
<memleak>
it has to be 5.4 because we're using RTAI
<memleak>
(real-time kernel, preempt_rt not fast enough)
<memleak>
i maintain the rtai repository for linuxcnc. my only other option looks to be backporting support for meteorlake into 5.4 if i can't get vesa going
<Ermine>
Well.. I'd try to blacklist any fbdev modules that show up and try to get xorg up with modesetting ddx
<Ermine>
(so simpledrm driver is in charge on kernel side)
<memleak>
checking if simpledrm is in 5.4...
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<memleak>
nope, introduced in 5.14
<Ermine>
ugh
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<jenatali>
alyssa: Do you know how lavapipe does sparse?
<Ermine>
just in case, there's also #xorg channel
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<memleak>
thanks Ermine checking there too :)
<memleak>
never saw this memory error come up before
<memleak>
i'm going to try backporting simpledrm to 5.4 and see how much work it is
<alyssa>
I guess I can just .dynamicRenderingLocalReadDepthStencilAttachments = true, it's not like anything uses DRLR right hahaha? *sweats*
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<memleak>
nope.. backporting simpledrm is not feasible
<vsyrjala>
lumag: i guess i don't really care what as long it doesn't add some assumptions that trip up when drivers trigger modesets that don't need any extra state checks
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<DemiMarie>
memleak: why is preempt_rt too slow?
<memleak>
latency needs to be lower for this guy to control stepper motors
<memleak>
rtai is always lower
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<DemiMarie>
Have you considered using a completely separate RTOS for the motor control tasks? Staying on Linux 5.4 isn’t going to be feasible in the long term.
<DemiMarie>
This could be done with either dedicated cores hidden from Linux or with a separate microcontroller.
<zmike>
tarceri: pls make sure to assign your glsl fix today before the branchpoint
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<memleak>
Yeah, the real fix is to port LinuxCNC to EVL/Dovetail for lower latency than what you'll get with PREEMPT_RT and it supports the later kernels, there's just no support for it in LinuxCNC
<memleak>
I'm trying a different approach with the vesa driver, going to do it in gentoo, maybe something screwy is happening with debian
<memleak>
I've never seen vesa not work in gentoo, not in my builds anyway
<memleak>
brb
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<jesperlundfrog>
I do not know much about quantum pre execution procedures (in the middle of looking at it from videos) microsoft simulated 4000qubits needed to break rsa, google told me. But packed exec intrinsics no longer have anything special involved, the stuff is encoded twice by compiler, so there is some compiler overhead involved only, the old intrinsics jabber wasn't for real, anyhow the
<jesperlundfrog>
compiler has quite a lot of overhead. I expect it to compile less than hour however and break the encryption if no mistakes in the routines in minutes on single computer. however logically taken the collisions can not happen, it needs to be enough big of computation sequence. so that 64bits are outputted correctly and decoded back, then read operands again, encode one level deeper and
<jesperlundfrog>
there we'd go again if no ipc than compilation and exection does not need to be fused as like not jit but operands could be loaded at compile time instead of runtime, there is actually no magic involved , compressed sequence can work well, on any number of qubits. It feels like you are as big as abortion leftovers than estonian and finnish anal heroes. Too much of asstrafficing to
<jesperlundfrog>
human trash like for laura keskinen, i do not care about this shitbag anymore, it was never like i was harassing her territory with my sexual partners making fraud and stealing money. That borderline human trash is not welcome with the wankspammers anal stuffers on my territory, you get it? I did not care more than about this only, what the asshole does not around me is her own
<jesperlundfrog>
business.
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<airlied>
karolherbst: moving here from other channel, could we move the intel subgroups into a faster to compile header?
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<karolherbst>
I'm working on pch support
<karolherbst>
that should speed it up a lot
<karolherbst>
the intel spirv files are generated roughly 8 times faster with pch
<Ristovski>
damn, quite a speedup
<karolherbst>
soo the plan is to simply precompile the opencl-c.h file
<karolherbst>
and then it doesn't matter
<karolherbst>
I have it working on the cli, but it's kinda more painful to get it working with libclang...
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<karolherbst>
it works.. nice
<karolherbst>
with PCH: time ninja src/intel/shaders/intel_gfx_shaders.pch src/intel/shaders/intel_gfx{80,90,110,120,125,200,300}_shaders.spv => real 0m0,482s
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<karolherbst>
without PCH: time ninja src/intel/shaders/intel_gfx{80,90,110,120,125,200,300}_shaders.spv => real0m1,471s
<karolherbst>
the difference in user is even more impressive
<karolherbst>
user0m7,584s => user0m1,205s
<karolherbst>
guess it's waiting more on IO than burning through the CPU
<karolherbst>
though the time spent is kinda variable
<psykose>
think it's just parallelism (slowest file went from 1,2 => 0,4, bit random), but they're all faster so the user goes way down
<karolherbst>
mhhh yeah fair
<karolherbst>
I mean, the PCH stuff needs to parse the header once single threaded
<karolherbst>
so the actual compile jobs start later
<karolherbst>
anyway...
<psykose>
means they're even faster than that 0,482 then for the slowest :)
<karolherbst>
yeah..
<karolherbst>
it's a small win
<psykose>
lines up with the -ftime-trace i saw for a lot of the smaller <5s files, they were mostly 50+% frontend
<psykose>
the huge 5 minute ones i think won't be impacted that much
<karolherbst>
it's just the intel shader stuff, but we do have a couple of more jobs using mesa_clc
<psykose>
er, not 5 minutes, 50 s
<karolherbst>
we should port the intel raytracing stuff over to mesa_clc as well
<karolherbst>
anyway.. best case without PCH: real 0m1,450s user 0m7,324s
<karolherbst>
best case with PCH: real 0m0,480s user 0m1,342s
<karolherbst>
dj-death, airlied: ^^
<karolherbst>
it won't make CI that much faster, but it's something :D
<psykose>
amd stuff has a lot of such files too if you wanna try too
<psykose>
i think the c++ especially
<karolherbst>
this is just for OpenCL C files
<psykose>
yea
<karolherbst>
host side PCH is kinda a build system mess I don't want to get involved in yet :D
<karolherbst>
the rules are funky, even for CL, but the environment is way more controlled
<karolherbst>
like at least with clang you can only have a single pch (though you can chain them by linking a new header pulling in a pch)
<karolherbst>
but I want to enable intel_subgroups in rusticl sooner or later, so I kinda want PCH support anyway
<alyssa>
that's fair
<alyssa>
pch applies to rusticl online compilation too?
<karolherbst>
not yet
<karolherbst>
would need to wire it up
<karolherbst>
it's a bit more complicated in online compilation, because you need one per combination of arguments I'm not sure yet which matter
<karolherbst>
I know that the CL version matters...
<alyssa>
ok, right
<alyssa>
nothing uses intel_subgroups with mesa_clc
<alyssa>
but. as a design decision, mesa_clc just enables everything to make it easy for mesa drivers to use
<alyssa>
and since mesa supports intel_subgroups, .. yeah
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<alyssa>
probably doesn't make sense to special case disable this ext in mesa_clc, either
<karolherbst>
especially if it's not that much slower with PCH, though I'll do some testing on it
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<karolherbst>
uhh.. after rebase that's going to be a bit more painful to support.. well.. still possible
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<karolherbst>
yeah.. so intel_subgroups disabled gives us real0m0,279s and user0m1,195s
<karolherbst>
intel_subgroups disabled with PCH is in the same ball park
<karolherbst>
slightly less user, slightly more real
<karolherbst>
so I think it will become faster with more users of the PCH
<alyssa>
karolherbst: so what should we do?
<karolherbst>
well.. I want the clc bits anyway. I think it also makes sense for intel_subgroups disabled, because the compile time with the pch not changed is massively faster in either case
<karolherbst>
=> faster development
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<karolherbst>
but it's opt-in anyway, so might as well keep it
<karolherbst>
let me remember which extension also needed it...
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<karolherbst>
ahh yeah
<karolherbst>
kernel_clocks
<karolherbst>
needs the big file as well
<karolherbst>
I'm sure the coop matrix stuff will also land there
<karolherbst>
anyway.. I think it's good to have it in place in case we have stronger needs for it
<alyssa>
sounds good
<alyssa>
will review tomorrow
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<mareko>
daniels: debian-ppc64el still has LLVM 15; it's OK to stop building radeonsi and radv for it, right?
<mareko>
jenatali: I wonder if it's better to build windows drivers with -Dllvm=disabled, that should be fine AMD drivers
<mareko>
in CI
<jenatali>
mareko: We build CL components there
<jenatali>
Those need LLVM
<jenatali>
mareko: I'm attempting to upgrade my local build from 15 to 19. Assuming it looks fine we should be able to bump CI too