21:35 <Degdag_Med[m]> lumag: I've been trying to get my panel driver to work on sm8150 , it's a non-DSC cmd mode panel on xiaomi k20 pro . I used last longbios branch . panel seem to initialize fine but it doesn't display anything only showing the early dmesg on the screen than it hang there without any refresh .

21:35 <Degdag_Med[m]> This is the log

21:41 <lumag> Degdag_Med[m], Let me take a look.

21:43 <Degdag_Med[m]> lumag: Thanks . if you need any more info about panel / DTS I can provide it

21:44 <aka_[m]> looks like dsi phy failing to init

21:44 <lumag> [ 0.264930] [drm:dsi_pll_7nm_vco_recalc_rate] DSI PLL0 returning vco rate = 0, dec = 0, frac = 0

21:44 <aka_[m]> well yea pll

21:44 <aka_[m]> is it tied to lets say gcc or rpmh?

21:45 <aka_[m]> maybe it lacks some source clocks

21:45 <aka_[m]> clk_core_reparent_orphans_nolock+0x88/0xc4 me not into stuff

21:46 <lumag> Degdag_Med[m], just for my understanding, is ther a splash from the bootloader, or there is none?

21:47 <lumag> also, at which point does -next kernel stop?

21:47 <Degdag_Med[m]> lumag: I'm using mu-sm8150 uefi bootloader for booting . no splash screen .

21:48 <Degdag_Med[m]> Let me take a video for you

21:48 <lumag> I see.

21:48 <aka_[m]> lumag: is there chance some power gets cut off so he can no longer access phy and it shows timedout on read?

21:49 <lumag> So, I'd not bother with -rc1, Marijn[m]'s rework of TE handling is only in linux-next, landing for 6.5

21:49 <lumag> Also let me sketch a patch which should at least attempt to fix the VCO

21:51 <aka_[m]> lumag: i was wondering, what do you think about cosmetic changes in gcc drivers?

21:52 <aka_[m]> i noticed some gcc drivers have clocks names like gpllX_early/aux/main yet enable mask does not align with these

21:52 <lumag> aka_[m], which changes?

21:52 <aka_[m]> on msm8953 there is gpll0_early which have BIT(0) enabled

21:52 <aka_[m]> its MAIN output

21:53 <aka_[m]> this layout appears to be common on these older alphas and non-alphas(8976/8916)

21:54 <aka_[m]> i was trying to craft backport for msm-4.19 and got lost with names when tried to find same names in ds drivers and found there was not even single mention of _early

21:54 <aka_[m]> also based on some looking in other socs _early output is not affected by POST_DIV

21:54 <aka_[m]> sadly no docs so cannot be fully sure

21:55 <aka_[m]> there is PRE_DIV_RATIO which i have no idea what is exactly changing

21:55 <lumag> Degdag_Med[m], could you please try https://pastebin.ubuntu.com/p/hYFSNgzPKn/ ?

21:56 <Degdag_Med[m]> lumag: Sure

21:57 <Degdag_Med[m]> Degdag_Med[m]: The framebuffer here is from the DRM driver not any kind of simple or efi frambuffer

22:00 <aka_[m]> ok i see some diagram about starFive and on them pre-divider is placed inbetween source and transform block

22:01 <aka_[m]> so pre-divider might be one to modify reference frequency

22:09 <lumag> aka_[m], I'm not sure about backporting to msm-4.19

22:09 <lumag> Anyway, I took a glance at 3.18 vs mainline.

22:10 <lumag> Speaking in 3.18 terms: gpll0_main_div2_mm is 400 MHz, gpll0 is 800 MHz

22:10 <lumag> gpll0_clk_src is also set at 800 MHz

22:12 <lumag> Speaking about the mainline, it seems that gpll0_early rate is read from the hardare

22:12 <aka_[m]> lumag: could be some divider in between block input

22:12 <lumag> What is the rate of that clock?

22:16 <aka_[m]> lumag: my limited understanding is that it could either be other output of gpll0(there are few) or there is static divider between these multimedia rcgs

22:16 <lumag> If I understand correctly, from the mainline perspective, the gpll0_early_div is clocked at 400 MHz, while gpll0 is clocked at 800.

22:17 <aka_[m]> On 8937 register config have hardcoded divider for one of gpu gplls

22:17 <aka_[m]> And they model it as clk_fixed

22:17 <aka_[m]> It would be weird to have early on lower clock

22:18 <aka_[m]> Because early might be rate pre dividers

22:18 <aka_[m]> Main is for sure affected by post div

22:18 <aka_[m]> You can check cpu 8976 driver

22:19 <aka_[m]> It has early at programmed pll rate and main on /2

22:19 <aka_[m]> And config does write post_div value

22:22 <aka_[m]> On 8953 mainline it would be gpll0 is 800 early_div is 400 and gpll0 is 800 but read-only

22:22 <aka_[m]> And consumers only depends on read-only gpll0

22:23 <aka_[m]> Still early there is wrong because it's main output

22:25 <lumag> aka_[m], and gpll0_early is also 800?

22:26 <aka_[m]> If it was used and enabled it could be

22:27 <aka_[m]> If bit(3) of user register is not set then early output is disabled

22:28 <aka_[m]> But if we have main output enabled at 800mhz then I doubt we can achieve 400 MHz on any other output

22:28 <aka_[m]> Like aux/aux2

22:29 <aka_[m]> If we had main and early enabled And post_div was set I would believe it can do 800 on early and 400 on main

22:30 <aka_[m]> Sdw429 driver in 4.19 have names much cleaner

22:34 <Degdag_Med[m]> <lumag> "Degdag_Med, could you please try..." <- This with the patch applied

22:37 <lumag> Degdag_Med[m], hmm, so PLL is not locking even if we configure it for the lowest possible rate.

22:38 <aka_[m]> Tho gpll3 wirh it's 0x1 bit messes because it should be auxY_output_mask and they didn't call it like that

22:38 <lumag> Just for my understanding, could you please add a call to dsi_pll_7nm_vco_recalc_rate() after calling the dsi_pll_7nm_vco_set_rate()?

22:38 <lumag> aka_[m], I'm trying to find a doc which would describe the clock tree or registers for a similar SoC

22:41 <aka_[m]> lumag: user register appears to be quite high level control register And layout of it is very similar regardless of generation

22:41 <aka_[m]> Config one is worse

22:42 <aka_[m]> Well even if some calls early main And set bit in reality it doesn't matter

22:42 <aka_[m]> Because these are only used to build final enable value inside clk framework

22:48 <lumag> aka_[m], ok. If that helps. for 8909 there is a pre-divider of 2. On the other hand, 8909 driver doesn't pay attention to early vs main outputs to be used as a source.

22:51 <lumag> Also, we mostly treat user register as read-only / static, there is no driver control over main / early / etc. being enabled or not

22:52 <aka_[m]> In few hours I'm going to check sm6115 sheet

22:52 <aka_[m]> This shows early is pre divider output

22:53 <lumag> aka_[m], you mean ,pre - postdivider?

22:53 <aka_[m]> And aux2 of gpll0 has post_div set to 0x1

22:53 <aka_[m]> Yea

22:53 <aka_[m]> Post div appears to not influence freq of early output

22:54 <aka_[m]> No idea about pre because I haven't found device whicb set it to anything else than 0

22:54 <aka_[m]> Which is no change

22:55 <lumag> aka_[m], I'm slightly puzzlled, since 8909 docs clearly describe /2 pre-divider, but I don't see it being accounted for in gcc-msm8909

22:55 <aka_[m]> 2 pre divider on which pll?

22:55 <aka_[m]> 8937 describe 2 post

22:56 <lumag> gpll0

22:56 <aka_[m]> They call it in "oxili" whicb is like gpu pll

22:56 <lumag> No, actual gpll0

22:56 <aka_[m]> lumag: I would recommend reading register

22:56 <lumag> no the oxili one

22:56 <lumag> I don't have actual 8909, just docs :D

22:57 <aka_[m]> On 8937 they say oxili have fused value of /2

22:57 <aka_[m]> Minecrell have 8909

22:57 <lumag> aka_[m], I see, pre_div is configurable

22:57 <lumag> Missed register name

22:57 <aka_[m]> Both are but not always

22:57 <aka_[m]> It appears qcom can fuse these down too

22:57 <lumag> well might be.

22:58 <lumag> Anyway, there is a bit for it.

22:58 <aka_[m]> If you find a way to connect like early you could bypass post_div limiter

22:59 <lumag> There is no special configuration for that. Some clocks have main as a parent, other have early

22:59 <aka_[m]> Yea

22:59 <aka_[m]> It's qcom who decide

22:59 <aka_[m]> If they want you to limit freq then can fuse div and connect just main

23:01 <aka_[m]> But these outputs are hard-wired mostly so if block is conected to early you need to enable early

23:01 <aka_[m]> You cannot enable main

23:01 <aka_[m]> I just have some issue with misleading names

23:01 <aka_[m]> That all

23:01 <lumag> I think early = before postdiv, main = main.

23:02 <lumag> And I don't know about aux/aux2

23:02 <aka_[m]> Yea

23:02 <aka_[m]> Aux probably also affected

23:02 <aka_[m]> So anything after early is affected by post div

23:03 <aka_[m]> Cannot say about what is affected by pre but probably reference clock(19.2mhz?)

23:03 <lumag> yes

23:08 <aka_[m]> On 8909 there is wrong bit set for apcs_gpll_ena_vote for bimc, enable mask says bit2 but bimc is bit(3), gpll2 shoudl be enable mask bit(2)

23:09 <aka_[m]> I don't have flat for 8909 but it's same on 8953 and 8916 so not going to be different on 8909

23:10 <aka_[m]> Well maybe before claimimg I shoudl check downstream first

23:13 <aka_[m]> Indeed it says 3

23:13 <aka_[m]> Weird