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<konradybcio> no hw
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<konradybcio> just like bengal
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<aka_[m]> they should just use 778g
<aka_[m]> i cannot believe diff in price is so big to justify not using it on 400$ device
<aka_[m]> 695 prob is as cheap as 662/680 because its everywhere now
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<calebccff> .. how does one go about porting a gcc clock driver from 4.14 downstream?
<calebccff> everything seems subtly different, and what i have done seems to result in the device resetting, which im not sure how best to debug XD
<aka_[m]> uh 4.14 should be pretty copy-paste
<calebccff> yeah it looks similar
<aka_[m]> reseting on gcc kinda weird indeed
<aka_[m]> which soc?
<calebccff> i assume it's that cuz it can't be anything else, it probes and then shortly after it just dies
<calebccff> sdm429w aka snapdragon wear 4100
<aka_[m]> gcc-msm8937
<aka_[m]> pretty much
<calebccff> it's apparently msm8939
<aka_[m]> imma have a look
<calebccff> aka_[m]: it has no gpll2
<aka_[m]> this driver is used on 8937/429 and more
<calebccff> aka_[m]: wdym "this driver"?
<calebccff> msm8937 upstream has additional GPLLs at least
<aka_[m]> cannot you just do [GPLL2] = NULL in override ?
<calebccff> aka_[m]:also the default gpll3 config is 750MHz instead of 1100MHz so that throws a lot of things off
<aka_[m]> gpll3 is dedicated only for gpu
<aka_[m]> and probably pll alone have L hardcoded
<aka_[m]> Junak/Vladly was doing some tests with debugcc on 625 and it didn't respect bigger L even if it seems to apply
<calebccff> aka_[m]: hmm ok
<calebccff> also just realised it could be smd-rpm clocks causing the reset
<aka_[m]> very possible
<calebccff> added those as well but uhh not sure how that works
<calebccff> could have missed some
<aka_[m]> they have additions for 8937
<aka_[m]> and 429
<calebccff> they have 439 not 429
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<konradybcio> isnt 429w 89*53*
<aka_[m]> no
<aka_[m]> 37
<konradybcio> eeh almost the same :p
<aka_[m]> nah
<calebccff> it's similar, i used msm8953.dtsi as a base anyways :P
<aka_[m]> 8952+newer plls=8937
<calebccff> notable differences there are half the CPU count, thermals are different, usb is different
<calebccff> yeah aka_ is right
<calebccff> aka_[m] what's with the soft_vote_gpll0 thing in downstream? And the vdd_cx stuff?
<aka_[m]> i guess they use it for handling shutdowns of gpll0
<aka_[m]> vdd_cx is just power domain
<aka_[m]> rpmpd thing
<calebccff> oooh i see gcc-msm8939 models gpll0 as a vote clock, probably i should be doing that
<aka_[m]> from what i noticed they do .vote ones on non alpha
<aka_[m]> calebccff: do you mean something like "clk_regmap gpll0_vote" ?
<calebccff> yeah
<calebccff> but sdm429w has the gpll0_sleep_clk which is a vote clock
<calebccff> so
<calebccff> eh idk this is all very confusing to me still
<aka_[m]> it appears this "vote" exist on both old and new plls just clk_alpha_pll.h have those under .clkr->enable_reg / clkr->enable_mask,
<aka_[m]> but older clk framework require them as clk_regmap
<aka_[m]> on 8953 gpll0 there is no sleep_clk_src documentation
<aka_[m]> APCS_CLOCK_BRANCH_ENA_VOTE ADDRESS 0x45004 goes straight to 0x4500C
<aka_[m]> huh not even documented on 8937 either
<aka_[m]> kinda weird as it seems to be parent to gpll0_main
<aka_[m]> APCS_CLOCK_SLEEP_ENA_VOTE_ADDR A:0x1845008
<aka_[m]> no documentation anywhere somehow
<aka_[m]> no idea if there is input of "sleep" into apcs block
<aka_[m]> by default there is just this apcs_mux taking 0(XO) 4(GPLL0) and 5(APCS_PLL)
<aka_[m]> or its just some thing where hardware can dynamicaly gate clocks
<aka_[m]> or branches
<calebccff> aka_[m]: well it's not the clock driver that makes it reset :<
<aka_[m]> then you have few other options
<aka_[m]> rpm clocks
<aka_[m]> power domains
<aka_[m]> mmu
<aka_[m]> or reserved memory
<aka_[m]> or accessing any underpowered hardware block