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<apritzel>
MoeIcenowy, wens, smaeul: what's the problem with sunxi-fel on the D1, exactly?
<apritzel>
just that we need to upload RISC-V instead of ARM code?
<apritzel>
IIRC the FEL protocol stayed the same?
<apritzel>
what about the swap buffer dance? Is that compatible?
* apritzel
found Icenowy's github branch ...
<apritzel>
so looks like it's indeed just(TM) RISC-V vs. ARM code to upload, but this is tightly woven into the current code, so I see how this is laborious to refactor
<apritzel>
and if I got this right, we don't need the swap buffer dance anymore, since the IRQ stack is gone, and the other stack is using higher addresses already
<apritzel>
so did anyone start on this, in earnest? or are people just using xfel?
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<juri_>
hmm. allwinner sata appears to be iffy. this is odd.
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<apritzel>
juri_: was it ever sane?
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<juri_>
apritzel: looks like recent kernel breakage.
<juri_>
works in 5.10.34 and 5.10.43, broken in 5.10.60, and later.
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<montjoie>
time to bisect!
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<montjoie>
juri_: what is broken exactly ?
<juri_>
the messages about power domain are different, and the sata device never shows up.
<juri_>
just reproduced multiple times, on multiple banana pi pros, hooked to reliable power.
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<montjoie>
on my cubie2, sata seems okay on 5.16
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<smaeul>
apritzel: there are two issues 1) ARM vs RISC-V thunks, as you noted 2) data cache setup is wrong initially, so there are some CSRs you have to fiddle with to get MMIO working
<smaeul>
so yes, people are just using xfel at the moment
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<apritzel>
smaeul: thanks!
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