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<jernej> apritzel: I compared OPi zero2 DRAM configuration between BSP and mainline and it matches completely (minus calibration/training values, which are similar.)
<jernej> so no bug there, at least on my side
<jernej> I still think BROM might initialize something differently in case of FEL and SD boot
<smaeul> did you compare clocks and PRCM?
<jernej> no
<jernej> but I just noticed that while write and read training factors are indeed similar, they are almost consistent between runs of same type. I'll look into that procedures again
<jernej> I'll look into clocks and PRCM afterwards
<smaeul> I don't remember there being any code in BROM that would affect DRAM directly, only indierct things like bus clocks
<jernej> smaeul: I noticed that H6 and H616 PLL init code in boot0 binary first clears and then sets bit 0 in PRCM reg 0x310
<jernej> we don't do that
<jernej> do you have any idea what is function of this register?
<smaeul> yes, that's some analog circuit calibration procedure
<jernej> ok, so this could be important
<jernej> ah, and bit 2 is set too
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<jernej> smaeul: I compared H6 PRCM settings between boot0 and SPL and I noticed that register 0x07010244 is set. BSP U-Boot sources say it's PLL LDO configuration but all my attempts to set it failed.
<jernej> do you know if this register is somehow locked?
<jernej> maybe I just failed to program key correctly...
<jernej> ah, scratch that. it's configured properly. it's just that TF-A probably protects this region, so reading it returns all zeros.
<jernej> on images with BSP stack it's freely accessible
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<smaeul> jernej: right, TF-A protects the PLL registers. You can set this to 7 (or write it at runtime) to access them from NS world: https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/allwinner/common/sunxi_security.c#L36
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