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<jernej> apritzel: V5 DRAM certainly looks like DW DRAM controller, like a H5 one
<jernej> but I think it has a few of its own quirks
<jernej> but I see some A64 elements there too
<jernej> you can try with them and enable CONFIG_SUNXI_DRAM_DW_32BIT
<jernej> master priority should be simple to write, just dump registers from BSP
<apritzel> jernej: thanks, so far I was staring at the boot0 disassembly and trying that old link-in-libdram trick
<apritzel> that v0.60 libdram didn't work, though, at least not with the parameters taken from the v0.66 boot0 binary
<apritzel> but I can indeed try with H5/A64 ...
<jernej> yeah, I've seen in the past that they have to update DRAM lib so it works with new board designs
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<jernej> apritzel: try with H5 quirks with addition of A64 one in mctl_set_cr()
<jernej> but to actually do anything I would need HW and experiment a bit...
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