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<apritzel> Hi, does anyone have an idea about the DRAM controller in the V5? How close is that to other SoCs? Many parts of the design look close to the H6, so is it an H6 DRAM ctl with a few twists?
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<jernej> apritzel: good challenge for today's evening :) do you have link to BSP?
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<jernej> gamiee: thanks, but I actually need boot0 binary
<jernej> but I'm not sure if "eagle" device refers to V5
<gamiee> it's very likely, I don't remember
<gamiee> But the V5 was less open-source than V536
<gamiee> Might be better to take look on V536, there should be boot0 source code for it.
<jernej> well, apritzel asked for V5, so I don't think V536 will do
<gamiee> Yes, but V536 boot0 code might have also code for V5, but hard to say
<jernej> besides, there is usually no source for DRAM
<jernej> annoyingly, DRAM core is almost never the same, even between very similar SoCs
<gamiee> Oh :-(
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<apritzel> jernej: "challenge for tonight": indeed, I was just looking at the closest starting point ;-)
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<jernej> don't expect any code, but I should find some info
<apritzel> I gave up on DRAM code a long time ago, and I would probably not want to read it anyway
<apritzel> so yeah, just info ala: close to the PHY of X, but COM is like Y
<jernej> why did you give up? it's not that hard to reverse it once you figure out some basics.
<apritzel> I meant I gave up on finding source code for DRAM
<apritzel> instead relying on reveng
<apritzel> I think what I once saw was just a bunch of "writel(MAGIC_VAL, base + 0x42);" anyway
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<apritzel> jernej: and btw: http://wiki.lindeni.org/index.php/Lindenis_V5#Layout confirms that "eagle" is the apparently the codename for V5
<apritzel> and thanks for the link, the boot0.bin is indeed what I was looking for
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<jernej> hm... I think it's too much for today. I'll have some time on Friday
<jernej> anyway, there is ZQ calibration mentioned, which reminds me on H3, but that's not necessary the case
<gamiee> btw, is there any plans on taking a look on V85X series in terms of mainlining?
<gamiee> It seems the SoC will be used several boards.
<apritzel> gamiee: there are no "plans": all it takes is someone with hardware and the will to push through
<jernej> someone must take interest in it and cover basics
<jernej> the biggest obstacle is usually DRAM
<apritzel> but since the "V853 is a new generation of high-performance and low-power processor SoC" (our Wiki) I am sure there are many people lined up ...
<jernej> well, to be fair, V3 is also popular because it's inexpensive and (probably) easy to work with electrically
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<jernej> but certainly I don't have interest
<gamiee> oh, makes sense
<apritzel> jernej: sure, integrated DRAM relieves people from the tricky DRAM board layout issues
<gamiee> btw, V5, what "sun8iw" code it have? I can't find it now
<jernej> 12
<apritzel> sun8iw12p1
<jernej> gamiee: go to page for that: https://linux-sunxi.org/Allwinner_SoC_Family
<gamiee> oh, I was on the page, but somehow missed the table, thanks :D
<jernej> apritzel: do you actually have V5 board?
<apritzel> jernej: yes, machinehum somehow got me interested, and he sent me one
<jernej> I thought you're not interested in 32-bit SoCs anymore :D
<apritzel> yeah, but Allwinner leaves me little choice ;-)
<apritzel> and I thought supporting an H6 in 32-bit might clean up some code
<jernej> interesting :)
<apritzel> so sunxi-fel works now, also the UART in the SPL: the SPL stack pointer was using the H6 value of SRAM A2+80K, but the V5 has only 64K
<apritzel> no stack, no fun ...
<apritzel> and of course it ends with: "DRAM:Timeout initialising DRAM"
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<jernej> gamiee: indeed, thanks! it has debug info intact
<jernej> it's slightly older (0.60 vs. 0.66), but it doesn't matter that much
<gamiee> great! and no problem :)
<gamiee> well, there might be newer binary somewhere, but even this took me some time to find it on github :D
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<jernej> apritzel: I guess you can use above lib for initial work temporary
<jernej> apritzel: I see indications that this is DW DRAM controller, supported by dram_sunxi_dw.c
<jernej> but don't hold me on that
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