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<apritzel>
Hi, does anyone have an idea about the DRAM controller in the V5? How close is that to other SoCs? Many parts of the design look close to the H6, so is it an H6 DRAM ctl with a few twists?
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<jernej>
apritzel: good challenge for today's evening :) do you have link to BSP?
<apritzel>
and thanks for the link, the boot0.bin is indeed what I was looking for
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<jernej>
hm... I think it's too much for today. I'll have some time on Friday
<jernej>
anyway, there is ZQ calibration mentioned, which reminds me on H3, but that's not necessary the case
<gamiee>
btw, is there any plans on taking a look on V85X series in terms of mainlining?
<gamiee>
It seems the SoC will be used several boards.
<apritzel>
gamiee: there are no "plans": all it takes is someone with hardware and the will to push through
<jernej>
someone must take interest in it and cover basics
<jernej>
the biggest obstacle is usually DRAM
<apritzel>
but since the "V853 is a new generation of high-performance and low-power processor SoC" (our Wiki) I am sure there are many people lined up ...
<jernej>
well, to be fair, V3 is also popular because it's inexpensive and (probably) easy to work with electrically
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<jernej>
but certainly I don't have interest
<gamiee>
oh, makes sense
<apritzel>
jernej: sure, integrated DRAM relieves people from the tricky DRAM board layout issues
<gamiee>
btw, V5, what "sun8iw" code it have? I can't find it now