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<MasterR3C0RD>
At least on a quick re-review, it seems like that's the only difference that'd affect LPDDR4 and not DDR4
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<apritzel>
sorry, no luck, same result, with both "original" and adjusted TPR11,12 para1,2 values
<apritzel>
I will try to dump the registers after boot0, but it's a bit tricky, since FEL is not really working, due to the "secure boot" feature
<hazardchem>
oh and 20 for multikey with 4, 100, 101, and 102
<hazardchem>
whoops wrong chat sorry
<MasterR3C0RD>
apritzel: Shoot. Thanks for the testing though, I appreciate it. In the meantime, I'll do a more careful review of the code and see if there's any other differences
<apritzel>
MasterR3C0RD: thanks for all *your* work on this. I am quite confident we will find the culprit, eventually
<MasterR3C0RD>
I just hope it'll be sooner rather than later HAHA
<apritzel>
will continue later, this day is my favourite of the year: 25 hours! ;-)
<MasterR3C0RD>
So far I've caught a few more errors in drive/ODT setup and CA deskew; those could be part of the problem with the LPDDR4 code
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<MasterR3C0RD>
jernej: You worked on the H616 DRAM init code, right? Have you messed around with DDR4 on those devices?
<MasterR3C0RD>
I've been working on bringing up the A133's DRAM controller, which is similar to the H616, and I've gotten it working with DDR4 using parameters dumped from boot0; however when I tried to implement bank group autodetection I couldn't quite figure out how to detect the aliasing pattern
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<MasterR3C0RD>
Unlike columns, rows, and banks, bank groups seemed to exhibit aliasing at address1 ^ ( BIT(4) | BIT(6) ) when set to 2 bank group bits when only 1 is connected
<MasterR3C0RD>
s/set to/configured for/
<MasterR3C0RD>
apritzel: Whenever you're able and willing, I fixed a few more issues in my branch; hopefully one of those fixes is the last piece of the puzzle
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<aedancullen>
Has anyone tried a DSI display with pixel clock above 80MHz-ish on DE2 hardware? On a T113/D1 system I see a total hang during boot, possibly near sun4i_tcon0_mode_set_cpu when the TCON clock might need to be reparented if pll-video0 isn't fast enough. Need to get more logging
<codekipper>
any help with the graph card would be appreciated....I'm usually just fiddle with the registers so getting the drivers probing would be great.
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<MasterR3C0RD>
apritzel: That's a very good sign; something's making it to DRAM. Does that result stay static after multiple runs?
<MasterR3C0RD>
If it does, that likely points to aliasing, which would imply something's up with the DRAM parameters
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<MasterR3C0RD>
loki666: Interesting; I might look through the H616 code more, but it's possible that access to the DRAM blocks is getting blocked off before accessing U-Boot
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<MasterR3C0RD>
apritzel: If that's indeed aliasing, it's a very odd pattern for it to take; it would imply that DRAM+0x0 and +0x28EEA640 are aliased
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