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<MasterR3C0RD> There was an error in the odtmap setup, perhaps that's it. You can try the following change:
<MasterR3C0RD> @@ -133,11 +133,13 @@ static void mctl_set_odtmap(const struct dram_para *para,
<MasterR3C0RD> val = 0x400 | (temp2 - temp1) << 16 | temp1 << 24;
<MasterR3C0RD> break;
<MasterR3C0RD> case SUNXI_DRAM_TYPE_DDR4:
<MasterR3C0RD> - case SUNXI_DRAM_TYPE_LPDDR4:
<MasterR3C0RD> val = 0x400 | (para->mr4 << 10 & 0x70000) |
<MasterR3C0RD> (((para->mr4 >> 12) & 1) + 6) << 24;
<MasterR3C0RD> break;
<MasterR3C0RD> + case SUNXI_DRAM_TYPE_LPDDR4:
<MasterR3C0RD> + val = 0x4000400;
<MasterR3C0RD> + break;
<MasterR3C0RD> }
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<MasterR3C0RD> At least on a quick re-review, it seems like that's the only difference that'd affect LPDDR4 and not DDR4
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<apritzel> sorry, no luck, same result, with both "original" and adjusted TPR11,12 para1,2 values
<apritzel> I will try to dump the registers after boot0, but it's a bit tricky, since FEL is not really working, due to the "secure boot" feature
<hazardchem> oh and 20 for multikey with 4, 100, 101, and 102
<hazardchem> whoops wrong chat sorry
<MasterR3C0RD> apritzel: Shoot. Thanks for the testing though, I appreciate it. In the meantime, I'll do a more careful review of the code and see if there's any other differences
<apritzel> MasterR3C0RD: thanks for all *your* work on this. I am quite confident we will find the culprit, eventually
<MasterR3C0RD> I just hope it'll be sooner rather than later HAHA
<apritzel> will continue later, this day is my favourite of the year: 25 hours! ;-)
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<MasterR3C0RD> So far I've caught a few more errors in drive/ODT setup and CA deskew; those could be part of the problem with the LPDDR4 code
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<MasterR3C0RD> jernej: You worked on the H616 DRAM init code, right? Have you messed around with DDR4 on those devices?
<MasterR3C0RD> I've been working on bringing up the A133's DRAM controller, which is similar to the H616, and I've gotten it working with DDR4 using parameters dumped from boot0; however when I tried to implement bank group autodetection I couldn't quite figure out how to detect the aliasing pattern
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<MasterR3C0RD> Unlike columns, rows, and banks, bank groups seemed to exhibit aliasing at address1 ^ ( BIT(4) | BIT(6) ) when set to 2 bank group bits when only 1 is connected
<MasterR3C0RD> s/set to/configured for/
<MasterR3C0RD> apritzel: Whenever you're able and willing, I fixed a few more issues in my branch; hopefully one of those fixes is the last piece of the puzzle
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<aedancullen> Has anyone tried a DSI display with pixel clock above 80MHz-ish on DE2 hardware? On a T113/D1 system I see a total hang during boot, possibly near sun4i_tcon0_mode_set_cpu when the TCON clock might need to be reparented if pll-video0 isn't fast enough. Need to get more logging
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<apritzel> MasterR3C0RD: still failing :-( but at least it now reports 29818880 (0x1c70000) as the value read from the first word of DRAM
<junari> what do I need to do to make audio work over hdmi in h616?
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<junari> apritzel: thanks, it's much clearer
<loki666> apritzel: made some more tests with your patch, and script that changes the cpu freq on userland gov
<loki666> that was just before it crashed (again)
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<loki666> so, I think we can say that CPU transitions are working, but it has a side effect on something else crashing
<loki666> I don't think it's the DRAM, as I ran stress-ng on memory with perf gov without issues
<loki666> MasterR3C0RD: I tried to dump with mainline, but all I got was 0x00 for all dumps
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<codekipper> junari: I'm trying to put something that would be mainlineable here https://github.com/codekipper/linux-sunxi/commits/sunxi-wip/ but you can use the Allwinner code by enabling it here https://github.com/codekipper/linux-sunxi/blob/31f1d00d6b1dcea532d0f0d424a8ad17515caeb9/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi#L868
<codekipper> any help with the graph card would be appreciated....I'm usually just fiddle with the registers so getting the drivers probing would be great.
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<MasterR3C0RD> apritzel: That's a very good sign; something's making it to DRAM. Does that result stay static after multiple runs?
<MasterR3C0RD> If it does, that likely points to aliasing, which would imply something's up with the DRAM parameters
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<MasterR3C0RD> loki666: Interesting; I might look through the H616 code more, but it's possible that access to the DRAM blocks is getting blocked off before accessing U-Boot
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<MasterR3C0RD> apritzel: If that's indeed aliasing, it's a very odd pattern for it to take; it would imply that DRAM+0x0 and +0x28EEA640 are aliased
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