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<marcan>
... I'm an idiot. sigh.
<marcan>
jannau: thanks
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<sven>
marcan: sure, i'll do it this evening
<sven>
i can also include the commit that adds the watchdog node while i'm at it
<marcan>
sure :)
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<marcan>
just pushed aic2 with a cleaned up take on the AICv2 support. There's one thing missing: I'm not sure how to get the true supported die count from the hardware :/ (to compute all the register offsets properly)
<marcan>
I have a guess but I'm not sure if it's right...
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<marcan>
ah yeah, that gets used in the next commit
<marcan>
maz: yeah, heh
<marcan>
what apple do instead is... specify the event register offset in the DT
<marcan>
which I think I like even less
<marcan>
(that's the only register which would have to be computed based on max dies; its location seems to be after all the IRQ control registers, rounded to page size)
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<maz>
marcan: we need to find a way to expose the E/P affinities in DT one way or another.
<maz>
so that the PMU interrupts can be discriminated.
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<marcan>
maz: I was going to ask about that; isn't it the same IRQ anyway? why does the PMU driver need separate IRQs for E/P if they're percpu anyway?
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<marcan>
also, looks like the PERST changes haven't been merged yet? is anything holding that up?
<maz>
marcan: that's the standard big-little horror. the core PMU code uses the interrupt affinity to find out about the PMUs that are compatible. E/P PMUs are obviously incompatible (they count different things), so you have to segregate them.
<marcan>
ugh.
<maz>
otherwise, you can't tell. they all have the same programming model, and count events similarly numbered. but the semantics of the events are can be radically different (they are on ARM cores, less so on Apple).
<marcan>
aside: just pushed a bunch of DT schema changes to asahi, enough to keep the checker happy about all the t6k stuff except NVMe/SART. cc kettenis in case you want to take a look; I'll probably fire off all the easy ones (everything but AIC2) as a series tomorrow
<marcan>
maz: using IRQ affinity just seems like such a hack for this...
<marcan>
but anyway, I think Apple are probably going to stick with that Aff2 thing for quite a while, they use it all over the place (and so does m1n1)
<marcan>
so I'm okay with going with that
<maz>
marcan: big-little is a terrible hack overall. shame it has spread...
<marcan>
heh :)
<kettenis>
maz: now that it has spread to x86, you can share te pain with lots more people ;)
<marcan>
ha
<roxfan>
where in x86?
<ar>
roxfan: new intel stuff
<j_ey>
alder lake
<ar>
but at least one x86 cpu vendor still claims they won't do big.little ;)
<roxfan>
TIL
<marcan>
it's so amazing it broke some game DRM because it thought you were randomly swapping out your CPU
<marcan>
... and apparently Intel's official workaround is a BIOS hack to use the scroll lock key to disable half the cores. yes, really.
<maz>
the positive thing is that someone found a use for this key!
<marcan>
hey, I use it to trigger my screen lock!
<maz>
ah!
<ar>
you can also do the windows equivalent of taskset
<marcan>
scroll lock, screen lock, close enough right?
<marcan>
;)
<ar>
to pin the game in question to p-cores
<maz>
my laptop has a dedicated 'print screen' key. I use it to locate the mouse pointer...
<marcan>
heh :)
<marcan>
I use Pause to trigger krunner (i.e. quick run app/command)
<marcan>
Print screen does trigger screen capture
<marcan>
though... I have to shamefully admit I've gotten too used to the macOS command-shift-{3,4} thing, and I've started to replicate it on my Linux installs...
<marcan>
will be convenient once I actually move to these laptops though, since those definitely don't have a Print Screen key
<roxfan>
will they have diffrent cacheline sizes?
<marcan>
ok, off to sleep. Finally managed to catch up on a bunch of kernel stuff today... I believe tomorrow I have a SPI reversing stream to do, and a couple more kernel mails to read/send out.