ChanServ changed the topic of #asahi-gpu to: Asahi Linux: porting Linux to Apple Silicon macs | GPU / 3D graphics stack black-box RE and development (NO binary reversing) | Keep things on topic | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-gpu
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<skmp__>
o/ @lina
<skmp__>
@marcan send me your way to inquire about m1 gpu details
<lina>
Hi!
<skmp__>
is it an imgtec derivative? does it have anything in common with the powervr archspec or the MBX (I assume only trisetup)/SGX (maybe USSE?) architectures?
<skmp__>
AGX seems awfully in line with imgtecs naming
<skmp__>
(though I could be completely off here, ofc)
<lina>
Ah, the architecture is a direct descendant of SGX, but Apple replaced many bits. Alyssa is doing the userspace part, the shaders are completely different but the draw state stuff is apparently similar?
<skmp__>
intriguing
<lina>
The kernel side is completely different since Apple have their own in-house firmware managing the GPU, that we have to interact with
<skmp__>
I have no idea how SGX or MBX kernel sides are
<skmp__>
I've implemented though CLX2.1 in software and fpga a few times
<lina>
Definitely not an Apple AArch64 core running RTKit...
<skmp__>
(CLX is before MBX, was used in the dreamcast)
<skmp__>
and I was casually reading the open specs of 2017 that were provided by imgtec
<skmp__>
and got curious to see the architecure
<daniels>
lina: *direct descendant of RGX
<daniels>
though RGX and SGX certainly share more than MBX and SGX
<lina>
Ah right, sorry, I keep thinking of the device tree node
<skmp__>
I'm vaguely familiar with SGX (It's a generalization of MBX, which still keeps the same building blocks as CLX, but of course much improved/ refactored)
<lina>
(Which is sgx... I guess because maybe that was the first PowerVR GPU Apple used?)
<skmp__>
do they still have TA, ISP and TSP as blocks? :p
<daniels>
the very earliest ones shipped with MBX, but yeah, SGX and RGX look similar enough at the ultra low-level
<lina>
TA yes, ISP/TSP I don't know
<skmp__>
ISP was "image synthesis processor" (Z buffer)
<skmp__>
TSP was texture and shading
<lina>
The three pipelines the kernel sees they TA, 3D, and CP, and they map to VDM, PDM, CDM
<daniels>
skmp__: TA is still there and semi-ganged with 3D from a job submission PoV, but anything to do with I/O got massively refactored with VDM/PDM/PDS/etc/etc/etc
<daniels>
T&L obviously got replaced with programmable shading units
<skmp__>
I see
<skmp__>
still does internal Z buffer + span sorting though?
<lina>
Yes!
<skmp__>
cute
<lina>
Well, internal as in special-cased
<skmp__>
yeah
<skmp__>
dreamcast claimed to be able to do Z processing for 32 pixels 'at once'
<lina>
It's just tile memory on one end and RAM on spills (or if the user wants a real Z buffer)
<skmp__>
but only share 1 pixel
<lina>
But there is special purpose hardware around it
<skmp__>
yeah, that was handled by the region array
<skmp__>
it defined the tile list, where to pull in which buffers, that passes to render and from which object/parameter lists, and where to flush and what
<skmp__>
s/that/the
<lina>
There is a "parameter buffer", yes
<skmp__>
CLX could only handle triangle strips of up to 5 vertexes though
<skmp__>
I assume that's no longer a thing lol
<lina>
Which is a terrible name, Apple calls it the Tiled Vertex Buffer in the one public mention they have of its existence, which is a much better name
<lina>
I might go with their public name
<skmp__>
I mean, it makes sense if you follow imgtec naming
<lina>
Imgtec naming is... kind of terrible...
<skmp__>
it is the 'parameters' for the 'image' and 'shading' processors
<skmp__>
you're just 'configuring' the hardware
<skmp__>
it's just EE-based
<lina>
Like TA is actually running the vertex programs, and 3D the pixel programs but as an identifier it's horrible because it starts with a number
<skmp__>
that makes perfect sense though
<lina>
That might have made sense before programmable shaders but now... it's just vertex attributes...
<skmp__>
how else are you gonna bin them and generate the region array lists
<skmp__>
can do that only post-vs
<skmp__>
TA is supposed to slice in 32x32 blocks for the renderer to handle one by one
<lina>
I know
<skmp__>
(not sure on the sizes at this point)
<skmp__>
so it needs screen coordinates
<skmp__>
so it needs to run vertex shaders
<skmp__>
right?
<lina>
Of course it makes sense, but then it's not just the tiling part, and from a software perspective it's not good naming
<skmp__>
I don't think they care much about software
<skmp__>
one can tell from their drivers that much
<lina>
As evidenced by how Apple themselves mix together TA/VDM and 3D/PDM...
<skmp__>
lol
<skmp__>
so yea
<skmp__>
I'd like to write an emulator for it
<skmp__>
would that be useful to you?
<lina>
Hmm... I mean, most of the work that's left is just porting over my prototype driver to the real kernel on the kernel side. You could definitely emulate the firmware (it's just AArch64) if you wanted to LLE that, but I already get nice crash dumps out of it and there is tons of tracing so I'm not sure we'd get much more out of it?
<lina>
Maybe it makes more sense to emulate the actual rendering side? alyssa would know if that's useful for her
<skmp__>
yea that part
<skmp__>
I'm interested just in the rendering pipeline tbh
<lina>
Yeah, then maybe talk to alyssa ^^
<skmp__>
I've known CLX and MAXWELL, and read up on SGX/RGX and some AMD stuff
<skmp__>
where can I find them?
<skmp__>
(would be nice to do AGX emulator, I've written a pixel-level emulator for CLX only)
<lina>
She's around here sometimes, and also @alyssarzg on Twitter