marcan changed the topic of #asahi to: Asahi Linux: porting Linux to Apple Silicon macs | General project discussion | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Topics: #asahi-dev #asahi-re #asahi-gpu #asahi-offtopic | Keep things on topic | Logs: https://alx.sh/l/asahi
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<marcan> artemist: (modulo when they go and break betas, but yes, for release versions :))
<marcan> (don't use a macos beta as your iBoot/firmware bundle for a Linux install long-term)
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<pugguu[m]> artemist: thanks
<pugguu[m]> Guess its timma do a update
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<sven> marcan: soo... how do we call the SPRR register that unlocks bits in SPRR_PERM_EL0 after it has been locked down but which can only be written from EL1? :D (SPRR_UNK2_EL1)
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<pipcet[m]> I got a very minimal mmiotracer working using the stolen-core approach. Probably not too interesting, the HV is much better, but if anyone needs an mmiotrace right this very second, it might help :-)
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<sven> alright, so apparently this DAPF block sometimes sits behind the DART (i.e. device -> DART -> DAPF -> memory) and it's just a very simple address filter
<sven> it has 16 filters which each have a 0x40 byte long config space. first u32 seems to be configuration, second u32 seems to select the SID and then there are two u64s which are probably start and end pointers
<sven> no idea why that exists since they can already do all that filtering inside the DART itself
<sven> i still have to figure out the exact bits inside the config register though, maybe they are doing something special to the memory range
<maz> sven: unless dart and DAPF can be controlled by separate entities (kernel vs hypervsor)
<maz> sven: a poor-man stage-2.
<sven> oh.. good point.
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<pipcet[m]> so it might prevent you from writing to the page tables when the dart is in pass-through mode?
<sven> i'm starting to think that one of the pass-through bits i found in the DART space is actually "DAPF bypass mode"
<maz> pipcet[m]: among other things. but it implicitly assumes that memory isn't badly fragmented (which isn't usually true)
<pipcet[m]> maz: might be true for the kernel page tables.
<sven> and maybe, just maybe, DAPF allows to set memory attributes
<sven> config: 0x10300, sid: 01, from 022b45c000 to 022b45c003
<sven> config: 0x10100, sid: 01, from 0800c80000 to 0800d23fff
<sven> that's from the ADT. first one should be RAM, second one should be MMIO
<pipcet[m]> but if there's a bit to by-pass DAPF it might be something else entriely.
<pipcet[m]> (that's arm-io/dart-ne/mapper-ane/pio-range)
<pipcet[m]> * (that's arm-io/dart-ane/mapper-ane/pio-range)
<sven> the end of the range looks strange though
<pipcet[m]> it's just a one-word range?
<sven> yeah
<pipcet[m]> from the ADT, there might be another one at 0x23b70c000 - 0x23b70c033, which seems even weirder?
<sven> maybe i can finally abuse the AES engine to look into the device address space now
<sven> there's a DAPF that's not inside the device tree just after the sio dart
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<tarzeau_> can mortals already boot asahilinux somehow (without extra hardware)?
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<tarzeau_> i get i can download https://github.com/AsahiLinux/m1n1 build it and start a linux arm64 kernel?
<tarzeau_> ah need serial usb
<pipcet[m]> just standard USB-C <-> USB-A works now
<tarzeau_> but requires a second machine or terminal... and someting like screen /dev/ttyS0
<tarzeau_> i'm fine waiting to have something on the local screen
<pipcet[m]> you'll get a logo right away, but having the second machine to chain-load the kernel is really handy. But, again, no special cable required. I don't own one.
<tarzeau_> the logo, and what about a local console?
<jannau> usb cdc acm doesn't work for the kernel though. the framebuffer works, input requires usb support in the kernel
<tarzeau_> ahhh i can use an usb-c to usb-a to another linux computer and that as terminal
<jannau> or support for the laptop keyboards
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<pipcet[m]> tarzeau: well, you can also chainload the corellium kernel if you just want to see whether it works on your machine, but that's not asahi linux.
<tarzeau_> jannau: yes!
<jannau> yes, but that doesn't work for the kernel yet. marcan is working on a minimal hypervisor which will provide a virtual uart to a second cdc acm interface
<tarzeau_> pipcet[m]: guess i'll be waiting
<tarzeau_> what i never understood is how people use linux in a vm like qemu, virtualbox or parallels. i couldn't get any to work
<j`ey> on m1?
<tarzeau_> yes
<j`ey> did you build qemu with the required patches?
<tarzeau_> openemu and dosbox work though
<marcan> sven: SPRR_PERM_MASK_EL1?
<jannau> the resulting system is not that useful as there is no storage or network support. i.e. you can boot a kernel and initramfs
<tarzeau_> j`ey: nope i wasn't able to build qemu i think, and virtualbox isn't even available. parallels i got that special beta, but nothing with debian nor ubuntu
<tarzeau_> jannau: ah, pointless
<j`ey> tarzeau_: well, uh, you building qemu with patches, just worked for me
<jannau> tarzeau_: patched qemu works fine for me since december
<tarzeau_> j`ey: current maaster? and where to find the patches?
<marcan> jannau: the hypervisor can do stupid serial emulation right now which should work for earlycon, I'll improve it to not be that stupid soon so it can serve as proper vserial
<marcan> was going to work on that and mmiotrace today, but emergencies took over my day...
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<jannau> marcan: I'm working on using a second cdc interface as vuart
<j`ey> marcan: where is the serial emulation?
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<marcan> tarzeau_: https://mac.getutm.app/ works on macos
<sven> marcan: i suspect that there will be another one for the EL1 perms though
<marcan> j`ey: there's a commented out #self.p.hv_map_vuart(0x2_35200000) in hv.py
<marcan> sven: accessible from.. EL2?
<sven> i'd guess s
<j`ey> marcan: thx
<tarzeau_> marcan: thanks for the pointer. /me tries
<marcan> sven: and you mean not like the VHE stuff?
<marcan> like something that unlocks EL1 perms?
<marcan> sven: I would bet DAPF is for GXF
<marcan> GXF needs to protect itself from DMA
<marcan> the kernel would be dealing with DARTs, no?
<marcan> or does GXF also handle DART paging?
<sven> i'm pretty sure PPL also handles DART paging
<marcan> ah
<marcan> then yeah, shittyhv?
<marcan> would require guests to have contiguous RAM though...
<marcan> and no paging
<marcan> seems kind of lame
<sven> it's weird
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<sven> i'm fighting against the AES engine to see if i can make it work there
<pipcet[m]> sven: does dart handle read-only/read-write permissions? maybe it's for that?
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<sven> dart handles that
<sven> marcan: (3,6,15,3,0) can unlock bits in PERM_EL0 and (3,6,15,3,1) can unlock bits in PERM_EL1
<sven> both writable until the lock bit is set in SPRR_CONFIG
<sven> so... SPRR_EL0_PERM_MASK_EL1 and SPRR_EL1_PERM_MASK_EL1? :D
<marcan> just EL0_MASK I guess, too long otherwise?
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<marcan> though EL1 should be EL2 in EL2 mode because VHE
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<marcan> which is just confusing as heck
<sven> yes :/
<sven> ugh.. this is going to be seriously confusing
<marcan> so how about SPRR_SELF_MASK_ and SPRR_LOWER_MASK_
<marcan> or even just SPRR_UMASK_ and SPRR_PMASK_
<marcan> since we already have UXN and PXN as de facto names for EL0 and "whoever is above"
<marcan> though Apple likes to use KERN for the key stuff
<marcan> so KMASK works too
<sven> oh dear, there's also a mask for el2 i think
<marcan> yeah but that's just SPRR_KMASK_EL2 then
<sven> (which is useless because VHE, but still)
<sven> (erm. no. i'm just confused)
<marcan> SPRR_KMASK_EL2 _EL1 _EL12 and SPRR_UMASK_EL1 (and _EL2 and _EL12 iff that one is split)
<sven> yeah, that sounds the least confusing
<marcan> bbl, dinner
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<marcan> pipcet[m]: if you want quick and dirty mmiotrace, all you need is
<marcan> (on top of the thing I just pushed to support reg-reg offset mode for loads/stores)
<marcan> that gets it to a point... where it loads a floating point register from mmio (yes, really)
<marcan> so I guess I'm goingt to have to add emulation for that
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<svenpeter> lol
<svenpeter> Which device exposes a float in its MMIO region? :D
<j`ey> svenpeter: the suspense is killing me!
<marcan> sven: not sure, pushing a dynamic ADT reg lookup thing into the yak shaving pile for tomorrow
<marcan> for now though I just bypassed those ranges, and also removed the PCIe nodes from the DT corresponding to the type C port the HV owns (xnu really didn't like dangling phandle refs)
<marcan> and now we're back at pmgr kills me, except due to flushing issues I don't see the final mmio poke, so the next yak shave push is to add a flush function to the dwc code, but also while I'm at it I might as well look into doing the serial port properly... then emulate that properly...
<marcan> (also fixed some bugs in hv_vm)
<roxfan> real float or just a vector reg?
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<marcan> not sure, I only looked at the load :)
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<pipcet[m]> marcan: cool, I'll have a look tomorrow. For now, I've got some mmiotraces to look through :-)
<pipcet[m]> svenpeter: the SMC puts floats in the MMIO region, but I wouldn't have thought those were actually loaded as floats.
<jannau> marcan: I started adding a second acm interface for the virtual uart. not working yet
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<pugguu[m]> When is next stream
<pugguu[m]> Or better yet how long will it be so i know when to watch the replay so i can skim through it
<pugguu[m]> As i useally do
<j`ey> pugguu[m]: i would guess in the next few days, there was meant to be one today, but life got in the way
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<pugguu[m]> j`ey: okay thanks
<pugguu[m]> Was just curious cus i had been waiting all day for it lmao
<pugguu[m]> Wondering what was going on
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