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<airlied> jenatali: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/issues/1055 is part of where const got lost for me
<airlied> there's a few things linked from there
<jenatali> Ugh
<jenatali> I... don't really like that translator
<jenatali> I don't have something better, but I don't like it
<airlied> so much lack of ABI and things work by happy accident
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* airlied fixed const by setting setPreserveOCLKernelArgTypeMetadataThroughString
<airlied> and parsing the strings
<airlied> though I think my wrapper changes broke something else :-O
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<airlied> okay opencl cts api/basic/compiler are all passing for me now with my current hackfest :-P
<airlied> (granted I've turned off images and 64-bit)
<airlied> 64-bit->doubles
<HdkR> Anything special about 64bit?
<HdkR> Beyond regular shader compute 64bit problems I guess :)
<airlied> doubles fail some tests wierdly
<airlied> i.e. segfault inside my compute JIT code
<HdkR> oops :D
<airlied> I suspect cosh(fp64) is doing something strange :-P
<HdkR> Signaling NaN being mean or something?
<airlied> might be calling a library funciton
<airlied> or some global lut
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* airlied is trying to get to at least a CL 3.0 baseline then I can add back the features
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<tjaalton> mattst88: it did get built though, though there's one build test that fails (lp_test_arit) but it isn't fatal for the pkg build
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<shfil> iirc, gcn 1.1 has a hardware based dsp, is there any sdk to use/access it?
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<tomeu> airlied: btw, just a heads up that I'm moving the deferred command stuff from lavapipe to src/vulkan, for drivers for GPUs with cmdstreams that cannot be emitted without knowing the framebuffer
<daniels> emersion: re KMS logging, you could write your own arbitrary markers to /dev/kmsg
<emersion> daniels: interesting, but only writable by root it seems?
<emersion> which makes sense
<emersion> can be useful when i'm debugging something, but not too much when i'm asking users for a log file
<daniels> yeah, if it's readable as non-root then you might be able to do reads before/after each commit and pull that in to your gamescope logging?
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<emersion> doesn't seem like it's world-readable
<emersion> dmesg is restricted nowadays
<emersion> thanks for the pointers still
<emersion> (the question wasn't for gamescope, it was for sway :P )
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<melissawen> danvet, is the sched dependency series still missing acks? I want to rebase v3d changes on top of that sched changes already...
<melissawen> at least I think that names won't change
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<airlied> tomeu: oh interesting, glad it useful beyong lvp
<airlied> beyond
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<danvet> melissawen, no tested-by yet from etnaviv
<danvet> also I think a tested-by/reviewed-by from robclark would be nice
<danvet> atm I think there's only some minor adjustments to comments and commit message I need to make
<tomeu> airlied: will have to remove some lvp-isms, guess there was no problem falling back to the vulkan types
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<danvet> karolherbst, dropped my thoughts on your mail
<danvet> usual disclaimer: might not apply, feel free to ignore :-)
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<karolherbst> danvet: cool thanks!
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<zmike> pepp: I think I finally got the last of the problem cases fixed...will look at updating the MR again soon
<zmike> I'm checking it out on radeonsi now though and noticed an odd issue
<zmike> how is z24s8 supposed to be sampled from in gallium semantics? it looks like radeonsi just treats this as z32 always?
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<danvet> can you take care of this?
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<MrCooper> zmike: IIRC depth(+stencil) formats sample depth, stencil-only formats sample stencil
<zmike> my brain hurts too much right now to think about it very deeply
<zmike> I slapped some duct tape on it for now and moved on
<imirkin> there's an esp annoying bit with sampling depth where in glsl you want the single depth value, whereas in FF (and ARB programs?) you want it as (0,0,0,x)
<imirkin> simplest if you just return it as (x,x,x,x) and let swizzling solve any problems
<mareko> z24s8 is really just z24,z24,z24,z24
<mareko> x24s8 is s8,s8,s8,s8, that's the swizzle
<mareko> then apply the sampler view swizzle
<imirkin> agreed.
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<jekstrand> How nuts would it be to get an Android builder in CI?
<jekstrand> Even just an NDK build would be sufficient. Just enough that we can stop breaking the Android build.
<jekstrand> s/we/I/ πŸ˜‚
<alyssa> nuts
<jekstrand> πŸ₯œπŸ”©
<krh> we have that
<krh> for freedreno
<alyssa> krh: oh hi
<jekstrand> Can it be in Mesa CI?
<krh> it is
<jekstrand> Can we build the Intel drivers in that build?
<krh> alyssa: hi!
<krh> jekstrand: I think we should
<jekstrand> krh: I suppose you're probably doing an ARM build there, though. So we'd probably need a different CI for x86 Android drivers.
* jekstrand files an issue and hopes for magic: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5211
<krh> jekstrand: yeah - should be easy enough though, we stubbed out enough of the Android SDK that we can build test the drivers without extra deps
<krh> jekstrand: yeah, it probably needs a bit of anholt magic
<krh> best I can do is wave my hands around
<jekstrand> πŸ‘‹πŸ‘‹πŸ‘‹πŸ‘‹πŸ‘‹πŸ‘‹
<ajax> the intel driver needs to get itself prepared to build on non-x86 anyway
<jekstrand> ajax: Yeah.....
<jekstrand> Or maybe we can get some of those IBM subsidiary people to do it. :P
<krh> ajax: well, that's a bit of a teaser
<ajax> krh: no it isn't. xe is a pcie device, you can plug it into arm64 machines.
<jekstrand> You can also plug it into LE POWER but we're never going to support that. :P
<ajax> or powerpickle or riscv or whatever
<jekstrand> But, yes, arm64 is a real use-case.
<jekstrand> And maybe LE POWER
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<jekstrand> (It's BE we're never supporting, sorry)
<ajax> i literally have zero inside info here, i'm just saying it's no longer bolted to an x86's MCH
<jekstrand> We also have to not assume SSE4.1 misc places.
<jenatali> I read LE POWER as "le power" with a French accent and it was very confusing for a minute
<jekstrand> :D
<krh> oh is Intel making a discrete GPU...? I'll believe it when I can buy is :-P
<ajax> that's unfair, you can't buy anything right now
<jekstrand> lol
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<ajax> i should just rip off the arch exclusions and throw it at koji and see what breaks
<alyssa> krh: Intel's discrete GPU will be released in the year of the linux desktop
<krh> alyssa: aka when wayland is ready
<alyssa> yep
<ajax> alyssa: this is funnier if you remember that the i740 existed
<ajax> and, arguably, more true
<alyssa> random question - any reason we don't use SPDX license identifiers in mesa but we do in kernel drm?
<imirkin> alyssa: because greg kh stuck random SPDX headers on all files in the linux kernel, of which drm is a part?
<alyssa> imirkin: fair enough
<jekstrand> krh: Oh, so you did the freedreno one! I'm assigning the issue to you. :-P
<imirkin> (ok, that's probably slightly unfair ... not _completely_ random ... but definitely not 100% accurate)
<krh> jekstrand: the commit says it's for tu, anv and radv
<jekstrand> krh: Then how do we keep breaking the Android build? :sob:
<krh> good question
<krh> jekstrand: looks like main only tests -D vulkan-drivers=freedreno,broadcom,virtio-experimental
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<alyssa> poor anv
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<jekstrand> Oh, I see a comment about how we don't have expat. I think we fixed that.
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<mareko> I'm contemplating compiling 2 versions of a huge templated radeonsi file just so I can have native POPCNT there
<alyssa> uhm
<dj-death> jekstrand: we created a stub for the batch decoding
<mareko> the default gcc version is too slow
<dj-death> jekstrand: intel_batch_decoder_stub.c
<jekstrand> mareko: Oof
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<imirkin> mareko: it's not part of x86_64? :(
<mareko> no
<imirkin> much sad
<jekstrand> mareko: Optimizing bitset walks?
<imirkin> yeah, looks like it's part of sse4 (well, separate bit, but coincides with cpu's)
<jekstrand> Wow, Intel didn't get it until Haswell. :(
<imirkin> jekstrand: nah, it was there earlier
<jekstrand> Time to delete IVB support from ANV. :P
<jekstrand> Oh, no, it's LZCNT that's HSW+
<imirkin> right
<imirkin> IVB support can stay in ANV ;)
<jekstrand> lol
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<imirkin> jekstrand: that said, you _should_ probably force ivb+ flags for compiling anv
<jekstrand> Hrm.... I should make us set -march appropreate for each per-generation compile.
<imirkin> i doubt it'll make a huge difference, but it's easy and safe
<mareko> imirkin: what about ryzen+dgx?
<imirkin> mareko: does not exist
<imirkin> :)
<krh> jekstrand, dj-death: just flip anv back on and give it a try then?
<alyssa> jekstrand: that's cute :)
<jekstrand> krh: Does Android seriously not have zlib?
<krh> jekstrand: do you need it without dumping?
<jekstrand> No, but the dep goes all the way up to src/util so it's a real pain to decouple
* jekstrand wonders how the ARM drivers do it
<imirkin> what do you need zlib for?
<jekstrand> The genxml we embed is zlib-compressed
<jekstrand> We don't actually need it at runtime if we don't have batch decoding
<imirkin> ahh, it's for batch decoding. i see.
<imirkin> that wasn't immediately clear why you might need the genxml
<alyssa> can't tell if my code is broken or the hardware
<jekstrand> Why not both?
<alyssa> wise.
<jekstrand> Nah, just snarky
<imirkin> but also wise :) assuming that there's only a single bug is why debugging goes wrong
<alyssa> jekstrand: looking like maybe booth
<alyssa> There is a buggy interaction between opaque output (bypassing the blender) and dithering with formats with <8 bits per channel (i.e. rgb5_a1)
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* cwabbott fixes xfb bug and then immediately purges xfb knowledge
<imirkin> cwabbott: can you teach me how to purge knowledge?
<jekstrand> cwabbott: If only it were so easy....
<cwabbott> well, it's more aspirational
<jekstrand> Uh, oh.... Sanity jobs aren't running for some reason. :(
<cwabbott> judging by how much knowledge I apparently purged since implementing GS streams for turnip, I think I did a good job
<jekstrand> lol
<imirkin> it all just sticks around for me :( like scars
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<alyssa> i find childhood memories easier to purge than details of the IEEE 754 spec
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<Sachiel> replacing one traume with an even bigger trauma
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<shfil> also pumping lemma causes holes in brain
<shfil> from cs this and ieee 754 I'm not able to forget
<alyssa> shfil: you don't want to prove things are irregular?
<ajax> who has an opinion about vulkan device uuids?
<shfil> alyssa: I like, but we had tasks like this "Determine if language X a) is regular (construct minimal finite machine and justify it) b) is context-free but not regular (show it's not regular and make pda with justification of its correctness) c) show it's not context-free"
<alyssa> Oof
<ajax> this in re !12311 where i'm supposed to return the same device uuid from egl as from vulkan
<shfil> usually on exam there were 2 tasks like this and construction of parser (for example lalr)
<ajax> but i don't really have a way to do that? because one i don't think we're consistent across vulkan drivers and two an EXTDeviceEXT doesn't have any real driver state so it's not like i can call down to the driver for the answe
<jekstrand> ajax: I may have opinions.
<jekstrand> ajax: Why does EGL want device UUIDs?
<emersion> jekstrand: sharing state between EGL and Vulkan
<emersion> ajax: imho the "EGLDeviceEXT is generic and doesn't need any driver info" stance is getting a bit annoying
<emersion> i have other cases where EGLDeviceEXT would need to probe the driver
<emersion> to query the render node being used for instance
<jekstrand> What extension is this? And was it written by Nvidia people? (probably)
<emersion> also this one i suppose? https://github.com/KhronosGroup/EGL-Registry/pull/108
<emersion> kmsro really makes all of this fun
<emersion> s/kmsro/renderonly/
<alyssa> :3
<jekstrand> emersion: Oh, so you're the one who asked for them to correlate. :P
<emersion> ah, yes
<emersion> it would make my life so much better :P
<jekstrand> Sadly, it makes life a real PITA for the people who have to provide those IDs.
<emersion> is it that much of a hassle?
<emersion> well, apart from mesa's weird stake on EGLDeviceEXT
<emersion> i imagine you coudl just have a single UUID generator in src/intel/ for both anv and iris
<jekstrand> We do
<jekstrand> intel_uuid.c
<emersion> ok, nice. then what's the issue?
<jekstrand> But it requires opening the DRM file descriptor and making kernel calls.
<emersion> indeed
<jekstrand> Not sure if that's a problem for EGL
<jekstrand> Generally, I kind-of hate the Vulkan UUID system.
<jekstrand> Maybe "hate" is too strong
<jekstrand> I get why it's useful. But it's always seemed fragile to me.
<emersion> because it's complicated to get them right?
<jekstrand> And the rules are complicated.
<emersion> right
<jekstrand> It's supposed to persist across reboots, but what if you change your machine configuration?
<jekstrand> If you have two identical cards and swap them, are the UUIDs supposed to follow the card? Or can they get swapped?
<jekstrand> What if you change your RAM configuration? That means new UUIDs on Intel.
<emersion> that's a "port vs sink" issue
<emersion> ah, eh
<emersion> that's fun
<jekstrand> Yeah, the Vulkan spec has all sorts of weasel words so it only says they usually don't change and provides no hard guarantees whatsoever.
<emersion> "port vs. endpoint" maybe better for this case
<emersion> yeah
<jekstrand> What if you're running in a VM? Should the guest and host match?
<jekstrand> If they do match, is that a feature or a security hole?
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<jekstrand> In the datacenter world, some people want an actual HW UUID so that, when a GPU breaks, can look at vulkaninfo and then look up in a spreadsheet somewhere to figure out which machine to fix.
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<jekstrand> In the consumer world, a device UUID is a tracker. We don't want those.
<ajax> emersion: re generic egldevice: omg yes
<alyssa> jekstrand: loonix is spyware confirmed????
<jekstrand> Anyway.... Now you all know why deviceUUID is thorny and why I kind-of hate that it exists. :)
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<ajax> jekstrand: intel_uuid.c and freedreno_uuid.c do different things
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<ajax> so unless libegl can get this out of the driver itself, it also can't just copy whatever the driver does
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<emersion> would it be acceptable to load drivers on egl device enumeration?
<jekstrand> ajax: Yup. You have to get it out of the driver.
<alyssa> VNC is magical
<jekstrand> I mean, I guess we could probably stop hashing in the bit6 swizzle. It probably wouldn't cause any actual issues in practice.
<jekstrand> But oof
<ajax> emersion: i mean... probably. you're not going to enumerate them unless you intend to load something, and there's only one driver binary anyway....
<jekstrand> If we did that, then it'd just be PCI ID.
<ajax> i wouldn't create a screen or anything
<jekstrand> So a hash of PCI ID and PCI path would probably work for PCI-based devices.
<bnieuwenhuizen> wait, was it supposed to be a hash
<jekstrand> ajax: Currently, Intel requires a screen to get the UUID
<jekstrand> bnieuwenhuizen: Doesn't have to be
<emersion> it's just bytes
<ajax> jekstrand: you're being too clever with the bit6 thing, i think. at least from egl's perspective.
<robclark> for non-pci devices, there isn't really a way to get you a uuid without opening the device file
<robclark> (OTOH it isn't like you are going to have both a mali and adreno gpu on the same SoC)
<bnieuwenhuizen> robclark: who knows with our potential chiplet future?
<robclark> heh
<emersion> but could you have something like two mali drm devices on the same SoC?
<robclark> I wouldn't expect it.. maybe having separate 2d and 3d cores (but the former isn't going to have much to do with egl)
<jekstrand> ajax: If someone ever scrapes the contents of a VkDeviceMemory object and saves it to disk along with UUIDs, we may have a problem.
<ajax> jekstrand: if they did that without also keying their hash to the driver uuid? i'd call that a sin.
<bnieuwenhuizen> or they better be using modifiers
<ajax> *shrug* i don't really care how the driver does it, and _ideally_ it would be by calling down to the driver so it can do whatever it needs, even if that's often just "hash the pci address and device ids"
<emersion> agreed
<ajax> but that's also kind of a lot of work when all i really want right now is the DeviceQueryString bit
<ajax> no good yak goes unshaved i guess
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<emersion> is it really that much work?
<jekstrand> ajax: Yeah, but if they pull out a stick of RAM and reboot, they'll get the same driver UUID since the driver hasn't changed but, as far as memory tiling goes, they have a different GPU now.
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<emersion> "just" need to establish a new DRI driver extension for EGL devices, plumb gallium…
<ajax> you'd get the same driver uuid if all you computed that from was the git hash
<jekstrand> We could probably move that to the driver UUID, though. I'd have to look at the rules.
<ajax> but that's the place where i'd stash things like swizzle conventions
<jekstrand> There are other cases too where "is it the same GPU" requires kernel interactions.
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<jekstrand> But those only affect shader compiles and that's allowed to change at the drop of a hat
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<dcbaker> bnieuwenhuizen: "b2b1e8e40a radv: Use correct signedness in misalign test." doesn't apply at all to the 21.2 branch, the function it patches up isn't in the branch
<dcbaker> what would you like me to do about it
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<kisak> dcbaker: hmm? it applied cleanly to my 21.2.0 PPA build without alteration.
* kisak goes and checks it
<dcbaker> For me the entire function becomes an insertion
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<bnieuwenhuizen> dcbaker: I think it got moves from src/amd/vulkan/radv_cmd_buffer.c
<bnieuwenhuizen> moved*
<dcbaker> I did some `git grep` and couldn't find it, let me look again
<dcbaker> well sure enough, my git grep-foo failed me
<bnieuwenhuizen> you found it now?
<dcbaker> yeah, it did move
<dcbaker> now why can't git figure that out...
<bnieuwenhuizen> cool, thanks!
<dcbaker> This might be the dumbest git cherry-pick issue I've ever seen
<dcbaker> It can't figure out that the function moved in the same file
<kisak> ah, so the difference is that patch -p1 figured it out over here instead of git cherry-pick
<airlied> jekstrand: could.move.uuid gen to kernel
<ajax> now we're talking
<airlied> just have it in sysfs
<DrNick> you mean /proc/sys/kernel/random/uuid
<DrNick> oh a per-driver UUID nvm
<emersion> i mean that technically is a valid driver UUID :P
<alyssa> UUID=$(hexdump /dev/urandom | head -n 1)
<alyssa> the "u" stands for "UUID"
<alyssa> anholt_: looks like LAVA needs some changes for suite support..?
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<airlied> I think Windows does a uuid device id in the kernel level
<airlied> danvet: ooh merging greg trees, what fun :-P
<danvet> airlied, tbh I'm not sure we have to, the conflict looks very simple and will keep linus busy
<danvet> otoh it also doesn't hurt
<airlied> danvet: I'll pull it in and see how it goes :-P
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<danvet> airlied, https://lore.kernel.org/lkml/YPkwQwf0dUKnGA7L@kroah.com/raw <- I guess this is the actual pull you want to feed into dim
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<airlied> danvet: seems to work
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<jenatali> airlied: it does, I believe
* airlied ponders put CL CTS into CI for test basic/api at least
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<jenatali> airlied: it'd be even better if we could add it as CI for the SPIRV-LLVM-Translator
<jenatali> But I'm onboard with putting it in ours. We've got CL piglits already
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<alyssa> jenatali: x q no los 2
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<mdnavare> danvet: airlied: Do we know if with AMD Hybrid gfx, they support the clone mode with displays connected on DG + IG
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<mdnavare> danvet: How can this be supported in general in KMS, since now the same buffer needs to scanned out across device boundaries and it cannot be pinned to just lmem or smem
<airlied> mdnavare: I think clone in that scenario is just the compostior creating two scanouts with same content
<airlied> or one GPU has a shadow copy that is synced from the main compositor
<airlied> but I can't say I've ever tried/tested anything like that
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<mdnavare> airlied: Yes the concern is that if it has to scanout on IG and DG then the buffer needs to be on smem as well as lmem, since the DG cannot scanout from smem so how does that work
<agd5f> mdnavare, hw doesn't support it. IG can't scan from dGPU vram and dGPU can't scan from sys mem.
<agd5f> plus, it's likely the 2 GPUs have different tiling requirements
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<alyssa> jekstrand: this is probably obnoxious but is (('fabs', ('ftrunc', a)), ('ffloor', ('fabs', a))) valid? πŸ˜‹
<mdnavare> agd5f: So this use case where displays connected across IG and DG in cloning mode is not supported by AMD?
<jekstrand> alyssa: Uh.... maybe?
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<jekstrand> krh: Ugh.... This Android build is getting annoying. It tries to build via a cross file but with the regular build scripts. The regular build scripts build tests. Our tests require expat because, hey, we test genxml. :-/
<jekstrand> This might need some anholt_ magic...
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<robclark> jekstrand: maybe disable those tests if with_platform_android?
<robclark> or maybe there is a way to check for expat dependency?
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<karolherbst> what are current OpenGL drivers do once they notice the GPU context is gone? I know that some drivers try to recover, but what are the ones doing which do not try such an attempt?
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<agd5f> mdnavare, I think most compositors handle it automagically
<robclark> karolherbst: in userspace or kernel? drm/msm attempts to replay submits after the faulting one.. userspace does nothing (other than report the context-lost if the application asks)
<karolherbst> robclark: userspace
<agd5f> mdnavare, just another case of cross GPU multi-head
<imirkin> robclark: but userspace gets away with it because kernel replays submits ... and the context isn't completely gone, just that submit failed
<robclark> right.. I'm not sure how/what userspace could try to do.. kernel seems to be the better place to handle that
<karolherbst> robclark: well.. sure, in our case nouveau reaps the channel
<karolherbst> but because we don't have this "wait on this fence ioctl", we do busy waiting
<karolherbst> it's stupid, I know
<karolherbst> but anyway
<karolherbst> once we detect that our channel/context is gone, we have to handle it somehow
<imirkin> really the "Wait on this fence" thing should be an ioctl
<imirkin> rather than being done in userspace like we do
<karolherbst> yeah, it should be
<imirkin> the kernel can wait on it with an interrupt
<imirkin> so it wouldn't have to spin
<imirkin> ("with an interrupt" -> "by making hw report an interrupt when the fence is reached")
<karolherbst> well if the kernel would busy loop that would already be better because checking for a dead channel there is essentially for free :O
<karolherbst> but yeah...
<karolherbst> but other drivers also don't have this GPU context thing as nvidia does
<karolherbst> so the question is a different one anyway
<karolherbst> and it maps terribly to other drivers
<karolherbst> maybe "how do you handle the case once submissions from userspace can't be worked on anymore"
<imirkin> hw contexts are definitely a thing
<imirkin> in non-nvidia hardware
<karolherbst> sure, but differently
<imirkin> but they don't magically die forever
<imirkin> (afaik)
<karolherbst> yeah.. dunno for sure
<karolherbst> but I think none other driver hands out a GPU context if userspace asks for one
<airlied> I'm broken on the inside, please somebody fix me.. ruh roh
<robclark> imirkin: for added fun, in adreno land (and I guess amd too) "context" is something completely different.. it is really the context or state for a given draw
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<imirkin> on nvidia it's the register state backing + mystery
* karolherbst gives WD-40 and tape to airlied
<airlied> anholt_: marge having issues or gitlab?
<robclark> yeah, it's the register state backing on adreno too.. but you can have different parts of the pipeline chewing on different draws each looking at their own "current" view of the register state
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<HdkR> For when duct tape doesn't work. Gorilla tape
<robclark> airlied: I think anholt is out this week.. maybe daniels can look?
<daniels> as ever, links really help please
<imirkin> daniels: cgit is unresponsive :)
<daniels> wooho
<daniels> airlied: just looked and no logs for your failure but is generally working totally fine, just try again
<agd5f> yeah, on AMD hardware, the context is a pipeline state. The CP firmware handles the context state rolls to keep everything pipelined.
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<agd5f> There are also GPUVM contexts on AMD hardware which represent a GPU virtual address space
<agd5f> Those are explicitly controlled by the driver
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<imirkin> on nouveau (and nvidia blob), the driver ties gpu vm + hw context state together, but technically they're unrelated
<imirkin> but in practice, since the hw context contains tons of VA addresses, probably not a great idea to mix and match :)
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<karolherbst> imirkin: well, but you can create a new context and keep the old vm
<imirkin> yea
<alyssa> airlied: I'm looking at IEEE 754 compliance of fpow
<karolherbst> alyssa: uhhh
<karolherbst> why?
<alyssa> meh
<imirkin> if that doesn't call for duct tape, i don't know what does...
<alyssa> AFAICT, the fpow lowering we have in NIR is wrong for some of the special cases.
<karolherbst> alyssa: correct
<karolherbst> but
<alyssa> but probably nothing cares except for CL, and for CL we call out to libclc unless native_ or half_ is used, so it's fine?
<karolherbst> it's easy to fix
<karolherbst> alyssa: we have correct lowering in codegen.. wait
<alyssa> jenatali: ^ as well
<imirkin> karolherbst: we have a 0*x = 0 mul variant
<karolherbst> alyssa: the yeah is that the MUL has to flush denomrs
<karolherbst> *denorms
<imirkin> i don't think that's generally available
<karolherbst> s/yeah/key/
<imirkin> karolherbst: dnz != ftz
<imirkin> karolherbst: dnz = zero wins
<karolherbst> ohhhhh
<karolherbst> right
<alyssa> imirkin: we do as well, that fixes a bunch of special cases
<alyssa> but what about, like
<alyssa> pow(0, k) = +inf
<karolherbst> alyssa: so we need a mul in nir with a "zero wins" behaviour
<karolherbst> alyssa: that's fine
<alyssa> where k is a negative odd integer
<karolherbst> The result is undefined if x<0 or if x=0 and y≀0.
<imirkin> ---^
<imirkin> that.
<alyssa> I'm looking at the IEEE 754 spec, what are you looking at?
<imirkin> don't do that. :)
<karolherbst> alyssa: the glsl spec
<alyssa> I imagine OpenCL has stricter rules..?
<karolherbst> let's check
<alyssa> (With the NIR lowering, you get log2(+0) = +inf, +inf * k = -inf, exp2(-inf) = +0)
<alyssa> ..I think
<jenatali> alyssa: You can look at the libclc implementation
<alyssa> wait log2(0) should be -inf
<alyssa> is this bifrost being stupid
<karolherbst> alyssa: yeah.. for CL you should just use libclc pow
<imirkin> all i know is that inf - inf = log(2)...
<alyssa> -inf & k = +inf, exp2(+inf) = +inf is ok. right..
<karolherbst> hence CL to have powr
<mdnavare> agd5f: How does the compositor solve the issue here of scanning out the same buffer on IG as well as FG i mean across multi GPUS? Does it kind of maintain 2 copies somehow? But that means the driver doesnt need to do anything special here?
<alyssa> jenatali: what about for half_pow(r)
<karolherbst> alyssa: the hardware isn't precise enough for pow anyway
<karolherbst> so you have to use libclc
<alyssa> Yeah, that's the real issue indeed.
<karolherbst> unless you have a real pow instruction
<karolherbst> and even that could fail
<karolherbst> but I doubt it
<mdnavare> agd5f: I understand that extended case it would just create 2 separate buffers and scanout from respective memories but clone mode how does compositor solve the cross memory problem
<karolherbst> I mean.. that any hw has real pow
<jenatali> alyssa: It's the same rules for specials, but for non-specials it just needs 10 bits of accuracy
<karolherbst> alyssa: so powr -> fpwo and pow -> libclc pow
<karolherbst> I think
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<karolherbst> but that's always the issue with lowering those buitlins
<karolherbst> same issue with sqrt
<alyssa> meh I'm going to say the NIR lowering with zero-wins is good enough :p
<karolherbst> alyssa: for powr maybe :D
<karolherbst> "powr Computes x to the power of y, where x is greater than or equal to 0."
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<alyssa> until someone pays me(collabora) for opencl i can pretend this doesn't exist..
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<karolherbst> alyssa: we already have libclc support :p
<karolherbst> ohhh wait
<karolherbst> we already use libclcs impl for CL
<alyssa> Ohh there's no half_pow, derp
<karolherbst> so...
<alyssa> got it got it thanks
<karolherbst> alyssa: ohh, that as well
<agd5f> mdnavare, Do wayland based compositors even support single buffer clone mode?
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<agd5f> I thought they always did per display buffers even for clone
<alyssa> karolherbst: Maybe it'd be clearer if we renamed the NIR op to fpowr?
<karolherbst> alyssa: meh
<karolherbst> but maybe?
<karolherbst> we can think about it once there is a GPU with native and correct pow support :)
<karolherbst> imirkin: did you know that we have nativ tanh support? :O
<karolherbst> since turing actually
<karolherbst> the hell
<HdkR> Turing is cute like that
<karolherbst> I was already surprised by that sqrt in maxwell2
<imirkin> karolherbst: i did not.
<imirkin> i barely know what tanh is.
<karolherbst> hyperbolic tangent
<imirkin> + instead of - iirc?
<imirkin> oh, yes, that explains it exactly.
<karolherbst> I think it's only important for CL actually...
<imirkin> tan = a / b. what's tanh? :)
<karolherbst> sinh / cosh :)
<imirkin> anyways, iirc the hyperbolic ariants are like e^x + e^-x instead of e^ix - e^-ix or whatever?
<karolherbst> something
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<karolherbst> "In mathematics, hyperbolic functions are analogues of the ordinary trigonometric functions, but defined using the hyperbola rather than the circle"
<imirkin> but what that signifies on a right triangle ... unclear.
<imirkin> i know what hyperbol*e* is ... what's a hyperbola?
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<karolherbst> sinh x = (e^x - e~-x) / 2
<karolherbst> ehh
<karolherbst> sinh x = (e^x - e^-x) / 2
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<imirkin> right. and sin has the i's in it.
<alyssa> imirkin: the shape of the shadow cast by a lamp that's open on both ends.
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<imirkin> alyssa: closest i remember is a hyperbolic parabolloid, which is a saddle.
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<karolherbst> imirkin: yeah, something like that
<karolherbst> I am wondering why tanh...
<imirkin> they don't really teach geometry (or spatial concepts) in USA, so i'm pretty weak on all that stuff.
<karolherbst> I am wondering if that's precise enough for CL actually
<karolherbst> and if a hw tanh makes lowering of the other functions much easier or so
<karolherbst> I am sure nvidia had a very good reason to put it in there
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* imirkin &
<karolherbst> ohh apparently machine learning uses tanh for... some stuff
<karolherbst> inside activation functions of neurons
<karolherbst> ehh
<karolherbst> without the "of neurons"
<alyssa> karolherbst: this is true
<karolherbst> interesting
<alyssa> although their use of it has nothing to do with the geometry
<alyssa> and everything to do with "well, it's vaguely S shaped"
<karolherbst> a pretty flat S
<karolherbst> but I am wondering if libclc uses tanh actually and if it can make lowering of the others faster as well
<karolherbst> mhh, at least not atm
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<jekstrand> robclark: Disabling the tests should work. Thanks!
<robclark> np
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<jekstrand> Oof. This Android CI MR is finding so many little things...
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