ChanServ changed the topic of #dri-devel to: <ajax> nothing involved with X should ever be unable to find a bar
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<Wally> Would I2C interactions with a display on the bus that the dri components interact with mess with dri operations?
<Wally> (the bus being of the monitors bus)
<imirkin> Wally: DRI? no. But DRM - yes. SCDC is accessible via that I2C bus, and screwing with that will potentially mess up the display.
<Wally> imirkin: is there a method to share that bus that has been implemented?
<imirkin> it's not about sharing/not sharing
<imirkin> it's about screwing up the monitor's settings
<imirkin> that bus is totally accessible to userspace via /sys
<imirkin> as for concurrent i2c transactions on the bus ..... not 100% sure
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<Wally> imirkin: so if I were to implement a ddcci driver using that bus, the monitors settings could be messed up
<Wally> hmm
<imirkin> well, that's a different i2c address iirc
<imirkin> scdc and edid are diff addresses from each other
<imirkin> iirc ddc is yet-another address?
<Wally> oh, so a ddcci driver wont mess with scdc?
<Wally> (idk what iirc means!)
<imirkin> lessseee... ddc/ci = 0x37, edid = 0x50, and scdc = ... can't find it quickly
<imirkin> SCDC = thing that controls scrambling for HDMI and some related settings
<imirkin> i'm sure it stands for something clever
* clever waves
<Wally> Status and Control Data Channel
<imirkin> scdc = 0x54
<Wally> I think
<Wally> so diff addresses
<imirkin> yeah
<clever> i think edid also shows up at 2 addresses, when over a certain size
<Wally> oh my god, the maintainers gave me a heart attack
<clever> one addr acts like a page#, and the other lets you view a 256 byte page?
<Wally> doing it without I2C made the code look awful!
<imirkin> Wally: a quick google search on the topic reveals https://www.ddcutil.com/
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<zmike> what in the actual tarnation is going on with stoney ci today
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<daniels> zmike: what’s wrong with it?
<mareko> M1 Ultra would actually be a really good product if it didn't cost $4,000
<mareko> we also don't know how the GPU scales with chiplets and non-compute workloads
<HdkR> It would be a really good product if everything worked on it in Linux out of the box :)
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<karolherbst> jekstrand: fyi, you can use "where Self : ..." when declaring traits, I am wondering if I am able to kill the macro with that
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<zmike> daniels: just seems insanely flaky the past couple days after being rock solid for weeks
<daniels> zmike: mm yeah, cristicc noticed that when pushing through some unrelated changes as well
<daniels> I wonder what broke it
<pepp> daniels, zmike: should have been fixed by https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15298
<zmike> mm I got some other flakes besides the stoney ones from buffer_map though
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<FireBurn> mareko: Hey, any idea why https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15209 might be giving me issues?
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<ajax> have we considered hooking up the ci build output to something like https://github.com/elfshaker/elfshaker ?
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<jekstrand> karolherbst: I don't think so. One thing that macro does is assert that the CLObjectBase and T pointers are the same. That can't be done with "where Self"
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<karolherbst> jekstrand: yeah.. I noticed it a bit later as well
<jekstrand> But, still, the macro is down to two very straightforward functions. Seems a lot more sane than a struct, impl, and half-dozen traits.
<karolherbst> jekstrand: atm looking at making queue Send and Sync.. but it seems like there are some deeper issues I did ignore :D
<jekstrand> karolherbst: :-/
<karolherbst> I am still wondering if we should keep PartialEq and Eq inside the macro, simply for consistency and having it available for all objects
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<karolherbst> the only issue I still have to figure out is Receiver and Sender not being Sync
<jekstrand> karolherbst: idk. I thought about it. The one or two places where it was needed, I just used pointers.
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<karolherbst> it does have implicit perf implications though
<jekstrand> I don't really like the hash sets anyway. I don't have a better plan yet. I just don't like them. :P
<karolherbst> It also matters for dedup
<karolherbst> uh... dedup only compares consecutive things.. argh
<karolherbst> jekstrand: anyway.. functions like dedup could throw out objects which have equal values, but are just different objects
<karolherbst> and that's something we can't really allow
<karolherbst> so overwriting PartialEq and Eq is kind of required to stay conformant
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<karolherbst> contains also checks for equality not identity
<karolherbst> so if we have 4 identical kernels...
<karolherbst> that's more or less my main reason to just have it for all objects
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<karolherbst> jekstrand: anyway.. I will keep a rusticl/main and rusticl/wip branch
<jekstrand> karolherbst: Have you promoted the new wrappers to main?
<karolherbst> yeah
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<jekstrand> Cool. I'm probably going to do some more IMG review today and a bit of panvk and then I may get back to rusticl. Anything in particular, I should be jumping on? We kind-of need kernels to work before we can do much more.
<jekstrand> Unless I wanted to look at de-duplication deeper
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<karolherbst> heh
<karolherbst> there is unique() on iter, but it requires Clone + Eq + Hash :/
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<karolherbst> ehh wait, that's a crate
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<karolherbst> jekstrand: I think you have to accept, that Rust just uses HashMaps/HashSets for this kind of stuff. Crates are doing the same
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<jekstrand> karolherbst: Yeah, that's fine I guess.
<karolherbst> mhh, we also have to add Hash to the macro, otherwise it can cause random problems ... oh well... it could have been worse
<jekstrand> karolherbst: If we don't want to open-code de-dup everywhere, we can make the vec_from_arr or whatever I called it helper take a bool dedup parameter.
<karolherbst> mhhh
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<karolherbst> the issue is, sometimes we have to dedup inside the final container
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<karolherbst> like when collecting all kernels for all devices in a program
<karolherbst> but yeah.. we could add such a parameter I guess
<karolherbst> although I am not sure if we really have to do it...
<karolherbst> "Duplicate devices specified in devices are ignored." only thing I found in the spec
<karolherbst> that's for clCreateContext
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<karolherbst> uhh.. adding !Clone and !Copy might make sense as well as this is something we really have to make sure never happens
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<karolherbst> ehh wait.. one has to derive that anyway
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<karolherbst> jekstrand: one fun issue to figure out is why math_brute_force tests are crashing randomly
<karolherbst> ehh wait.. that was a use after free in the CTS... :/
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<karolherbst> jekstrand: I think I will implement running a kernel at the weekend or so.. should be doable.. I hope
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<karolherbst> jekstrand: if you are up to it you could implement some of the image stuff. Those tests don't depend on kernels afaik
<karolherbst> like implementing clEnqueueMapImage etc..
<karolherbst> or I deal with that and you look into kernels :D
<jekstrand> right
<jekstrand> Right now I'm trying to keep IMG from committing NIR sins. :)
<karolherbst> :D
<karolherbst> have fun
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<karolherbst> jekstrand: the only thing which I dislike about the new wrapper is the slight overhead for CLInfo :/ but there might be a way by improving cl_prop...
<jekstrand> karolherbst: You mean handling reference counts as a special case?
<karolherbst> no, I meant that Arc::as_ptr *::from_ptr dance
<jekstrand> For fetching the reference count?
<jekstrand> I'm still confused
<karolherbst> I'd like to just write cl_prop::<cl_context>(&prog.context) for CL_PROGRAM_CONTEXT
<jekstrand> Oh, for getting objects
<karolherbst> yeah
<karolherbst> but I think we could have an abstract impl for those with where...
<karolherbst> potentially
<jekstrand> Yeah, maybe
<karolherbst> will try it out at least
<jekstrand> I thought about having a cl_context::from_ref() which does that dance
<jekstrand> But the reference counting situation is horrible
<karolherbst> yeah, it is
<jekstrand> The fact that CL gives you a reference sometimes is just a disaster
<karolherbst> well.. the spec was written with C in mind :/
<jekstrand> I mean more that you shouldn't hand back a pointer and not hand back a reference
<jekstrand> It's all kinds of messed up
<karolherbst> mhh, true
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<ajax> glXMakeCurrent says it's not legal to call it between glBegin and glEnd
<ajax> i'm... not really seeing any code that enforces that?
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<ajax> literally no code on the client side that ever ends in raising GLXBadContextState
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<ajax> server side will raise it in a couple of cases, for indirect contexts, which you're not using
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<ajax> and weirdly only GLX has that constraint, EGL is silent on whether makecurrent is legal between begin/end
<ajax> which i guess makes sense since gles doesn't have begin/end at all
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<idr> I guess that makes sense... being that GLX nominally buffers the data between begin / end.
<HdkR> But you can use GL with EGL. Sounds like an oversight?
<ajax> HdkR: that's new in EGL 1.4, believe it or not
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<airlied> if you use egl and begin/end, it's a hole you deserve to fall down :-P
<HdkR> Oh jeez. I guess I never looked at an EGL version <1.4
<ajax> egl 1.3 was december '06 so i suppose you're forgiven for not knowing that
<HdkR> Fits, I only looked at EGL once ES 3.0 was a thing
<ajax> well. glx technically says calling any glx function in begin/end is undefined so the current yolocode is perfectly legal
<ajax> good. i can go back to not caring about this.
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<HdkR> oop, I just noticed that intel_clflush is being used on ARM hosts if you're building iris. Not sure if this was fixed in a newer version of mesa.
<HdkR> Will check once I get my local build done
<jekstrand> HdkR: Not sure what GPU you're planning to use that driver build on...
<HdkR> It's something that'll need to be fixed regardless :)
<jekstrand> Eventually, sure, but i915 doesn't even build on ARM so...
<jekstrand> I guess if someone wants to run shader-db on their M1 laptop
<dcbaker> daniels: (or others) has there ever been any attempt to add automatic labeling to gitliab issues?
<HdkR> Luckily I can ignore kernel space.
<jekstrand> dcbaker: mslusarz wrote a script. Last I checked, we just never got around to figuring out where to host it.
<dcbaker> that would be super useful for us (Intel)
<dcbaker> and me, in particular :)
<jekstrand> It'd be useful to everyone. We just need to figure out hosting. Maybe daniels know why it stalled?
<karolherbst> although not sure if I should drop that from_ptr, but including it gets complicated :/
<jekstrand> karolherbst: I kind-of like having cl_context involved
<karolherbst> I was thinking of adding a new trait to reverse the order, so the argument given can be something else, but I need to think about it a bit more
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<dcbaker> Oh, by the way, Jussi promised we'd get the structured sources work into meson 0.62, so that should make bindgen easier
<dcbaker> and the proc-macro stuff landed for 0.62 as well
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<idr> HdkR: And it's really a problem with indirect rendering... which EGL doesn't do at all.
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<HdkR> Oh right, indirect is a thing
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<daniels> dcbaker, jekstrand: yeah, there has - if someone can make https://gitlab.freedesktop.org/freedesktop/mr-label-maker into something with the usual workflow - CI pipeline builds a tagged container, container executes the entrypoint which checks for something to do, sleeps a minute, checks for something to do, etc - I'll get that deployed
<daniels> just not getting wide enough time slots to make that happen :(
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<dcbaker> daniels: I can probably justify working on that. Are there any docs on what needs to happen?
<daniels> dcbaker: hmmm, not really. I think it's mostly: if you give me a repo which produces a container which a) runs infinitely until it crashes doing the thing it's supposed to do, and b) takes access token + repos to monitor + tagging rules as a config file, then I can make that happen quickly
<dcbaker> daniels: okay, I'll see what I can do
<daniels> dcbaker: <3
<daniels> I'd so appreciate it, thankyou
<dcbaker> well, I need to be able to extract issues that apply only to intel drivers through the rest (or that other) API, so having something automatically create the tags is pretty important
<dcbaker> lol
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<dcbaker> Anyone have last minute objections to 22.0.0 getting released today?
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<Sachiel> yes, it should have been released on feb 22. Got get a time machine
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<dcbaker> Sachiel: blame covid
<FLHerne> nah, that's last year's excuse, disruptions resulting from the Ukraine crisis is the 2022 one
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<Sachiel> dcbaker was waiting for covid to stop being cool before he got it himself
<dcbaker> FLHerne: I watied until just before the Invasion of Ukraine started so I wouldn't have a conflict
<icecream95> New Zealand has been waiting for covid to stop being cool before trying to give it to all of us
<HdkR> dcbaker: No complaints from FEX-Emu side. With how little that matters :P
<dcbaker> HdkR: thanks! Always happy for a lack of complaints :D
<daniels> icecream95: unlike NZ to be slightly behind the curve!
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<karolherbst> "Returns a semi-colon separated list..." ....
<dcbaker> karolherbst: cmake?
<karolherbst> OpenCL
<karolherbst> apparently returning a semi-colon separated list for the kernels in a program was at some point a smart idea...
<dcbaker> Well, as long as they dont also return a semi-colon separated mapping...
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<jekstrand> karolherbst: tf?
<jekstrand> dcbaker: If you went and made that happen, I would be forever grateful!
<airlied> HdkR: got an arm board I can plug an intel card into? :-P
<HdkR> airlied: Sure. Slap it in an Solidrun or Nvidia Xavier
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<HdkR> Tegra Jetson Orin will also have a release date this month with GTC coming up
<HdkR> I'm planning on throwing a few Radeons in my Ampere Siryn server once it crops up. If kernel and userspace is ready then Maybe I'll throw an Intel GPU in it.
<karolherbst> jekstrand: yeah....
<agd5f> HdkR, PCIe can be a problem on ARM. the two big problems are: 1. some platforms don't support cache coherency with the CPU (required by the PCI spec) 2. platforms don't allow general remapping of PCI BARs for CPU access
<HdkR> agd5f: Luckily I don't care about those platforms
<HdkR> Xavier and Ampere Computing doesn't have this problem
<HdkR> Solidrun maybe?
<HdkR> I recall someone had some issues with radeon there but I think it was some random kernel bits that got resolved.
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<HdkR> I'll never advocate for someone to buy a Raspberry pi and try to stick a dGPU on to it.
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<agd5f> HdkR, lots of random ARM systems are missing whatever IP bits are required
<HdkR> Aye. Those platforms are basically limited to NVMe storage.
<HdkR> and wifi
<zmike> dcbaker: \o/
* dcbaker is just glad to have the .0 out the door
<mattst88> \o/
<mattst88> bumped in Gentoo :)
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<dcbaker> mattst88: \o/
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<ccr> \o\
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<RSpliet> /o/
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