ChanServ changed the topic of #dri-devel to: <ajax> nothing involved with X should ever be unable to find a bar
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<alyssa>
zmike: subgroup
* zmike
dies
<icecream95>
alyssa: You should have forked zmike before saying that, it wouldn't have been so dangerous then
<alyssa>
:D
<alyssa>
gdb ./zmike
<alyssa>
r
* karolherbst
dies
* icecream95
passes '-ex run' to avoid typing r
<karolherbst>
what I need is an AI setting breakpoints I want without having to actually type those
<icecream95>
That's called a segfault
<karolherbst>
I guess an AI adding segfaults is more credible
<karolherbst>
for v in self.variables_with_mode(nir_variable_mode::nir_var_uniform) :3
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<FireBurn>
It's been a bad week for Horizon Zero Dawn / PRIME gaming. Two kernel bugs, two mesa bugs and a bug in vulkan-loader
<FireBurn>
Are there any plans to add a PRIME system into CI?
<karolherbst>
with luck there already are some
<karolherbst>
would be interesting to know which of the runners have CPUs with iGPUs
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<alyssa>
cwabbott: This optimization might be too obscure/stupid to matter, but in principle `gl_PointSize = <dynamically uniform>` can be lifted into a preamble shader, saving O(n) memory bandwidth for the write and O(n) again for reading non-constant psiz
<alyssa>
and on Bifrost, allows IDVS to be used more often
<alyssa>
(Bifrost doesn't allow psiz writes with IDVS due to a hw limitation)
<alyssa>
wondering if that would be sane to implement with a backend hook into the preamble infra
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<cwabbott>
alyssa: there's nothing in there for moving output writes to the preamble
<cwabbott>
I guess you'd have to have your own pass to do that
<cwabbott>
we already have our own pass to push UBOs in the preamble
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<jannau>
I'm working on the drm driver for the display controller on apple silicon macs. The macbook pro 14"/16" models have rounded corners and a 74 pixel high cut-out (notch) at the top of the display
<jannau>
our initial strategy is to pretend that those top 74 lines do not exists
<jannau>
that's easy to implement for simple-framebuffer, just modify the fb pointer and the height
<emersion>
jannau: the preferred solution would be to have a hardware DB somewhere
<jannau>
I'm not sure how annoying that is to implement in the drm driver. maybe it's enough to modify the height in reported modes (just the native display resolution) and offset the start y position in the actual HW swap calls
<emersion>
and just make that info available to compositors
<emersion>
there is a thread about this on dri-devel
<jannau>
yes, passing the information along so compositors can make informed decicions where to display things is of course the preferred solution
<jannau>
but based on that thread it is going to take months/years before that is supported in the majority of compositors
<emersion>
that's not a good excuse to hack things away IMHO
<emersion>
i can type the wlroots part of it if you'd like
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<alyssa>
cwabbott: Sure, it'd have to be backend-specific anyway
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<karolherbst>
airlied: one thing I am wondering about how libclc caching is implemented in clover... how are we making sure that different devices are getting the same libclc or is it all the same?
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<karolherbst>
normally I'd expect the cache to be keyed per device anyway.. maybe I should just do that in rusticl and use it for everything :)
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<alyssa>
jannau: there are only like 5 compositors to care about *sweat*
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<karolherbst>
guess using get_disk_shader_cache is the way to go
<karolherbst>
alyssa: mhh, maybe? We do have encoding space for clamps on textureGrad and nir_lower_tex does say "We're ignoring GL state biases for now." when lowering _txd
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<alyssa>
karolherbst: Yeah, that's why I was confused
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* alyssa
wonders if there are piglits for this
<alyssa>
Passed: 17/38 (44.7%)
<alyssa>
that's, like, progress :-p
<karolherbst>
fun
<karolherbst>
I hope all fails are due to hw unsupported _txd ops
<alyssa>
currently we do lower_txd and are conformant
<alyssa>
trying to wire in the hw support though, since the lower_tex code is... ALU heavy.
<imirkin>
alyssa: tex-miplevel-selection piglit has grad tests
<karolherbst>
alyssa: I am sure the hw doesn't support all _txd
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<imirkin>
it doesn't on nvidia. but i think it does on most other chips
<karolherbst>
well.. at least not 3D
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<karolherbst>
imirkin: maybe, but there is a lowering pass explicitly for 3d tex grads
<alyssa>
imirkin: Ooh, that does seem to test the interaction
<alyssa>
thanks
<imirkin>
karolherbst: on nvidia? yes.
<karolherbst>
no, in nir
<imirkin>
oh
<imirkin>
i guess someone else had the problem then :)
<karolherbst>
somebody has put it there for a reason I think
<karolherbst>
:)
<imirkin>
i wonder how that works though. on nvidia we implement it by using some pretty low-level concepts...
<karolherbst>
check out lower_gradient_cube_map
<imirkin>
quadon/off, etc
<karolherbst>
the amount of options->lower_txd_* flags
<imirkin>
alyssa: that test takes 1000 different args, so try to look at how it's run in the tests/opengl.py file.
<karolherbst>
imirkin: tldr: it calculates the lod inside the shader and calls textureLod
<imirkin>
oh dear
<karolherbst>
yeah..
<imirkin>
i guess you gotta do what you gotta do...
<karolherbst>
but not sure if there is a generic way lowerint 3D _txd to 2D _txds without hw specific ops
<imirkin>
definitely not
<imirkin>
on nvidia we just stuff the "right" fake values into the various lanes and just call texture() :)
<karolherbst>
yeah...
<imirkin>
"oh look, magically the derivatives work out to what we wanted all along, who could have imagined"
<imirkin>
but that's not exactly portable.
<karolherbst>
I wonder...
<karolherbst>
maybe with shuffle?
<imirkin>
maybe with some of the advanced ops like that yea
<imirkin>
i dunno what all has become available with the subgroup exts and whatnot
<karolherbst>
I mean.. on supported archs we just shuffle and enable "quad mode" if that's a fitting term
<imirkin>
on all arch's...
<imirkin>
(for the non-natively-supported variants)
<karolherbst>
ehh right.. shuffle was an opt for maxwell
<karolherbst>
and kepler2?
<alyssa>
Passed: 28/38 (73.7%)
<imirkin>
there was always mov's with lanemasks
<alyssa>
...progress?
<imirkin>
alyssa: just 10 more...
<imirkin>
s/2/3/
<karolherbst>
mhh
<imirkin>
karolherbst: it's the same since nv50
<karolherbst>
yeah.. maybe I have to check what quadop actually does
<imirkin>
we use "quadop" which is like a shuffle
<imirkin>
it has alu ops built into it
<karolherbst>
or my knowledge contradicts what's in the source code
<imirkin>
but by being clever, you can get it ot od whatever
<alyssa>
2D/3D txd working, cube maps broken
<karolherbst>
mhh yeah
<alyssa>
apparently, the hw ignores cube maps for txd and treats them like 2D images for face 0
<alyssa>
which is... probably not right...
<karolherbst>
imirkin: ahh now I know why I am confused.. because the same code works on volta, but we don't have those fancy quadops
<karolherbst>
there is just "it's now quad op time" and nothing else
<imirkin>
hehe
<imirkin>
we've gotten a lot of mileage out of that code. surprising it works across all those gens with very few adjustments
<karolherbst>
yeah.. I think we don't correctly understand that quadop stuff :D
<karolherbst>
but somehow we got it right
<karolherbst>
anyway .. for volta it's really just put into quad op mode and do shuffles more or less, but what that quad op mode is? no idea
<karolherbst>
maybe really just bundling threads into quad and execute shuffles or maybe it's something more hw specific
<imirkin>
karolherbst: i never understood why recentering it on lane 0 rather than the "natural" lane made things work in vs
<imirkin>
but can't fight with reality
<karolherbst>
yeah... no clue
<karolherbst>
my only guess is that our understanding is wrong
<imirkin>
it's what the blob did, and what made tests pass, so ... yea
<alyssa>
Ooh my first instruction taking more than 4 registers of inputs, exciting!
<alyssa>
(^ of staging inputs, more than 6 registers total)