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<zmike> idr: I think your sparse tg4 MR can land now?
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<gawin> Kayden: I remember that once you've edited my commit in MR (to add rb), how did you do that? does gitlab create intermediate branches?
<emersion> you can just clone the branch locally, then edit and push
<emersion> if the MR author has checked the right box
<emersion> there's a button somewhere to display instructions to clone locally
<emersion> s/clone/checkout/
<gawin> been wondering how it's handled on privileges level (I usually cannot edit your forks)
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<emersion> there's an "allow to edit source branch" checkbox when submitting a MR
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<daniels> karolherbst: yeah, looks like it's missing a dependency on the container job
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<FLHerne> BAe 146 airbrakes are pretty radical for an airliner
<FLHerne> er, wrong channel
<Rayyan> lol
<HdkR> You right though
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<karolherbst> daniels: yeah.. I figured that out as well, but it's there in the .extends chain... oh well
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<alyssa> airlied: everything about !18136 makes me suspicious
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<JPEW> Ok, I figured out more on my virtio gpu problem: For some reason the virtio kernel driver isn't allowing mesa to allocate dumb buffers from /dev/dri/renderD128 (it returns EACCES). Is that normal?
<emersion> yes
<emersion> render nodes can't do dumb buffers
<emersion> dumb buffers are for KMS exclusively
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<JPEW> Ah, so mesa is probably falling into trying to allocate a dumb buffer because it can't allocate a non-dumb one from virtio?
<JPEW> (Even though this is impossible on a render node)
<Frogging101> hakzsam: What do you mean by RADV_CMD_FLAG_INV_CACHE?
<Frogging101> I see _ICACHE, _SCACHE, or _VCACHE
<hakzsam> oh sorry, missed one letter, it's VCACHE
<Frogging101> What's the WaW hazard here, by the way?
<hakzsam> I think if we don't flush these caches, the hw might write values from the previous dispatch
<hakzsam> in practice I think it won't happen because the copies will use CP DMA because they are very small, but it looks safer to flush
<Frogging101> Okay
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<dj-death> Venemo: dumb question on !18143, why can't we just assume a default value when we see a c = phi(some_undef_ssa, some_const_ssa) ?
<Venemo> dj-death: what do you mean by assume a default value?
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<dj-death> Venemo: essentially replace an undef by something that matches another branch
<Venemo> dj-death: for example, consider this pattern: "if (a) { b = ... } else {} c = phi(b, 0)" to make this work, ACO inserts an instruction in the else block that writes 0. this means that even though the else was empty, it can't be removed. to solve that, the new code transforms the phi to: "c' = phi(b, undef); c = iand(a, c')". thanks to the undef, now ACO doesn't have to add any code to the else block and the branch will be deleted.
<Venemo> I suppose this doesn't help backends that handle phis differently
<alyssa> Venemo: hm wait why iand
<alyssa> why not transform the phi to
<alyssa> "c' = phi(b, undef); c = bcsel(a, c', 0)"
<alyssa> you still get to delete the else block and coalesce the phi
<Venemo> in this case the bcsel would be more expensive than the iand
<alyssa> I guess the only difference is whether iand or bcsel is more efficient for booleans on your hw
<alyssa> right, ok
<alyssa> other way around on Mali
<alyssa> (Maybe Mali needs iand of boolean -> bcsel rules, hum)
<Venemo> if that helps you, I could change it to bcsel and optimize that to iand in the backend
<alyssa> I mean I don't handle undefs in the backend yet
<alyssa> I also have a lot of problems and this isn't one of them :p
<Venemo> for us, being able to delete the branch means we can also get rid of the instructions which manage the exec mask in that branch. effectively this means we can remove more than 1 instruction when we have this case
<alyssa> Sure
<alyssa> It helps every backend in theory
<alyssa> just requires smart undef handling and good idel in practice
<alyssa> isel
<alyssa> though maybe we should enable it as everyone and use the shaderdb as a carrot/stick to get backends to fix their RA :-p
<Venemo> we could of course handle this special case in the backend ourselves, but that's very tricky. or we could enable this part of the opt only in RADV
<alyssa> NIR is definitely the right place for it
<Venemo> basically I'm solving a defect in our phi handling by hacking NIR
<alyssa> How is it a hack?
<Venemo> well, I'm just sayin it feels a bit dirty that I solve a backend specific problem in NIR
* alyssa is curious how it affects backends that use nir_from_ssa + proper ssa_undef handling
<alyssa> intel, for ex
<Venemo> I guess that's a question for dj-death
<dj-death> I'm not knowledgeable enough on this part
<Venemo> can you run it through a shader db and see if it helps intel or not?
<dj-death> anybody can :)
<dj-death> thanks to intel_stub_gpu ;)
<Venemo> umm...
<Venemo> please?
<dj-death> heh
<dj-death> but it's hot here
<Venemo> or tell me how to use intel_stub_gpu
<dj-death> Venemo: you need to compile mesa with -Dtools=intel
<Venemo> I don't get what this is. is this an env var or a separate executable?
<dj-death> actually -Dtools=drm-shim,intel
<dj-death> Venemo: it's an LD_PRELOAD lib that stubs the i915 interface
<Venemo> and will this work with fossilize?
<dj-death> Venemo: it will make the mesa driver believe you have an intel gpu
<Venemo> ok
<dj-death> Venemo: yes, I've it for Q2RTX
<Venemo> okay, give me a few minutes
<dj-death> Venemo: there are example for doing a diff between 2 runs
<dj-death> in the README
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<glehmann> dj-death: I don't think you want to add the q2rtx .foz in that MR :P
* alyssa debating how much she wants to cry
<alyssa> (NIR rewrite of u_simple_shaders)
<alyssa> I really don't have time for this right now ... but TGSI architecturally can't encode non-float gl_FragColor which is tripping up panfrost
<dj-death> glehmann: there is another MR for it
<Venemo> dj-death: can I tell it which GPU I want it to emulate?
<Venemo> is that the -p
<dj-death> Venemo: I would go with tgl
<dj-death> -p tgl
<Venemo> ok
<dj-death> again not too familiar with undefs handling
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<Venemo> it's slow
<Venemo> but it seems to be working
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<alyssa> is augmenting TGSI easier? surely not ...
<zmike> pls just let it die
<alyssa> zmike: would u like to rewrite u_simple_shaders
<zmike> no
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<alyssa> boo
<alyssa> well it was worth a shot
<zmike> I respect the attempt
<alyssa> the problem is that the API is all TGSI too
<zmike> I don't understand tgsi and I don't want to
<zmike> nir 4 lyfe
<karolherbst> alyssa: hi!
<Venemo> alyssa: use ttn?
<alyssa> karolherbst: hi hello
<alyssa> Venemo: TTN loses information, that's the problem
<karolherbst> alyssa: how are you today?
<alyssa> karolherbst: I'm ok. Why do I feel like you're buttering me up to review rusticl
<karolherbst> alyssa: I honestly don't :D
<karolherbst> already got somebody to review it
<alyssa> woo!
<alyssa> zmike: btw, thank you for the mold MR
<alyssa> if I knew how nice mold was I'd have switched ages ago
<zmike> it's so incredible
<karolherbst> the linker?
<zmike> thank ishitatsuyuki though since he's one of the people working on it
<karolherbst> is it like 100x faster or what's the deal?
<alyssa> yeah
<alyssa> ishitatsuyuki: thank u
<zmike> it's at least 10x faster when c++ is involved
<zmike> maybe more
<karolherbst> nice
<zmike> cts linking goes from 30+ seconds to 1-2s
<karolherbst> best way to default to that?
<karolherbst> in meson I mena
<karolherbst> LD=mold or something?
<zmike> I just use `mold --run ninja`
<zmike> it wraps commands
<zmike> no need for meson options or whatever
<karolherbst> ahh, cool
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<alyssa> u_simple_shaders is so bigger, ugh
<alyssa> this is going to suck no matter what, isn't it.
<karolherbst> rewriting u_simple_shaders to nir?
<alyssa> yeah
<karolherbst> probably
<alyssa> even just the subset panfrost needs
<karolherbst> but parsing text TGSI also sucks
<karolherbst> why are we even doing it?!?
<alyssa> history :sparkles:
<karolherbst> :D
<karolherbst> probably
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<alyssa> maybe I should just stick a shader key at it.
<karolherbst> but as long as it allows us to kill TGSI, it's a good investment of time
<alyssa> the combinatorics just suck really hard.
* airlied wonders why tgsi can't do non-float outputs
<karolherbst> maybe because nobody wants to work on TGSI anymore, and those who would either didn't or left :P
<airlied> no like it can do them
<airlied> it's a typeless IR
<airlied> it doesn't care about float vs int, and I'm pretty sure drivers using it could handle integer render targets
<alyssa> airlied: that's what I mean
<alyssa> but NIR is typed so tgsi_to_nir claims all outputs are float
<alyssa> which breaks down real hard for int render targets.
<alyssa> and then NIR drivers need to ingest nonsense like
<alyssa> vec4 32 ssa_9 = (int32)txf ssa_8 (coord), ssa_7 (lod), 0 (texture), 0 (sampler)
<alyssa> intrinsic store_output (ssa_9, ssa_0) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=4 slots=1 /*132*/, xfb() /*0*/, xfb2() /*0*/)/* out_0 */
<Ristovski> zmike: Are you going to allocate all mold linker time savings to blog content?
<Ristovski> >finally, daily articles
<airlied> alyssa: remind me next week, I don't want to page in u_transfer_helper on the weekend :-P
<zmike> no
<alyssa> airlied: this is unrelated to u_transfer_helper :)
<airlied> alyssa: that was just a reply to your earlier comment :-P
<Ristovski> :(
<alyssa> aha
<alyssa> airlied: No, the current problem is just that Panfrost really wants to know at shader compile time what type shader outputs have
<alyssa> GLSL spec requires you to match types with fb formats and GLSL->NIR preserves that
<alyssa> TGSI is typeless and TGSI->NIR just bullshits everything as float
<alyssa> which is causing CTS fails for me on valhall
* karolherbst wondering how nvc0 dealt with this with pure TGSI
<alyssa> karolherbst: It's only a problem if your BLEND instruction depends on the src type (int/uint/float) but *not* the framebuffer format (then you just key the whole thing)
<alyssa> of the 4 archs I work on, only 1 is like that (valhall)
<karolherbst> ahh
* airlied is used to NIR being typeless as well
<alyssa> NIR is definitely typed..
<karolherbst> not the ssa values at least
<alyssa> at least store_deref/store_output are
<alyssa> vec4 32 ssa_9 = (int32)txf ssa_8 (coord), ssa_7 (lod), 0 (texture), 0 (sampler)
<alyssa> intrinsic store_output (ssa_9, ssa_0) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=4 slots=1 /*132*/, xfb() /*0*/, xfb2() /*0*/)/* out_0 */
<alyssa> the problem with this sequence is that a perfectly valid reading is:
<alyssa> sample the int values, reinterpret them as float32, and then convert the float values back to integers for the framebuffer format
<karolherbst> store_output is a mess :(
<karolherbst> alyssa: what's the nir_variable like btw?
<alyssa> float32, because ttn makes up the type
<alyssa> because the TGSI output is typeless
<karolherbst> mhhh
<alyssa> this is despite u_simple_shaders having the TGSI type right there and throwing it away
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<karolherbst> luckily for us it doesn't matter...
<karolherbst> alyssa: why not just treat is as raw data? or are there cases where you actually have to convert?
<alyssa> karolherbst: because the hw need to actually convert into the fb format
<karolherbst> or do you have to encode the type or something?
<alyssa> the float/uint/int is encoded in the blend so the hw conversion works
<karolherbst> mhhh "annoying"
<alyssa> BLEND.f32(0x3f800000) with R16_FLOAT framebuffer will write 0x3c00
<alyssa> BLEND.u32(0x3f800000) with R16_FLOAT framebuffer will write 0x7c00
<karolherbst> alyssa: can the right type derived from the TGSI or external information? Than I suggest ttn simply needs some adjustments to make all store_outputs to be correctly typed
<alyssa> not in general
<alyssa> because you could do uintBitsToFloat or intBitsToFloat
<alyssa> which I assume are both implicit in TGSI because, again, typeless
<airlied> yeah you'd need to add something to the output semantic
<alyssa> airlied: yep. so now you get to my "augment TGSI, rewrite core code to be NIR, or give up and add a shader key" dilemma
<karolherbst> alyssa: there are no implicit conversions afaik
<alyssa> those aren't conversions, they're reinterpretation
<karolherbst> well.. you don't need those either
* airlied would have thought shader key was the "proper" way to do it
<karolherbst> the instruction decides on how to interpret bits
<airlied> but I understand wanting to avoid it
<alyssa> airlied: both OpenGL and Vulkan specs are written to ensure you don't need a shader key for this
<alyssa> it seems really iffy to add one just because TGSI is dumb
<karolherbst> alyssa: I suspect no TGSI driver ever needed it
<karolherbst> so OUT doesn't have a type
<airlied> yeah no TGSI driver ever cared
<airlied> like SVIEW didn't grow a type for agse
<karolherbst> I suspect we'd have to add support for that to TGSI or safe the information until later for ttn
<karolherbst> and just use that stored type when emiting store_output
<alyssa> although.. Valhall does have a BLEND.auto32 that uses whatever type matches the framebuffer
<alyssa> which I guess is always safe, even for broken TGSI shaders ...
<karolherbst> alyssa: I assume we lose that information when going from GLSL to TGSI, no?
<karolherbst> ehhh.. wait
<karolherbst> those are builtin shaders
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<karolherbst> alyssa: which is the broken one for you?
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<alyssa> karolherbst: util_make_fragment_tex_shader with integers
<karolherbst> what's dtype when it's called?
<karolherbst> is it the correct type or something random?
<alyssa> (U)INT i assume
<alyssa> but dtype isn't plumb into the actual TGSI
<karolherbst> are you hitting it because of u_blitter?
<alyssa> yes
<karolherbst> mhhh
<karolherbst> annoying
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<alyssa> truly
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<alyssa> let's see if te BLEND.auto32 hack works
<karolherbst> it better be, otherwise fixing it feels like to be pain
<alyssa> 100%
* alyssa kind of wishes we had a nir->info.buggy_tgsi propert
<karolherbst> :D
<karolherbst> create one
<alyssa> (AUTO works)
<karolherbst> yay
<karolherbst> my other suggestion would be to track down the source of the store_output and find the first typed instruction
<alyssa> that doesn't work
<karolherbst> :/
<karolherbst> we should ditch TGSI for good
<karolherbst> :D
<alyssa> oh, nice, we have that flag...
<alyssa> info->fs.untyped_color_outputs
<karolherbst> :D
<alyssa> Meh, my name was more creative :-p
<karolherbst> but does that actually help you or will you just always use AUTO?
<alyssa> It does help!
<alyssa> It lets me use auto for broken TGSI shaders and proper types otherwise
<karolherbst> wondering if using proper types has any advantages.. but I guess it has otherwise it wouldn't be there
<alyssa> Dunno tbh
<alyssa> it's more readable
<zmike> jenatali: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18118 can you check out this build failure
<zmike> it seems like either windows jobs should be running more often to catch this or they shouldn't be building whatever files these are
<alyssa> karolherbst: See the top 2 commits of https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17841
<karolherbst> ahh
<jenatali> zmike: Yeah looks like the addrlib stuff wasn't part of the file lists for Windows CI
<jenatali> Hm no, that can't be...
<jenatali> Nothing there's changed
<alyssa> !cd
<jenatali> zmike: fatal: unable to access 'https://github.com/microsoft/DirectX-Headers.git/': OpenSSL SSL_connect: Connection was reset in connection to github.com:443 :(
<jenatali> Looks like the runner's having issues... either that, or GitHub is
<zmike> so the addrlib thing is unrelated?
<jenatali> Seems that way. I think the runner's just having problems, probably needs to be disabled
<zmike> :/
* zmike makes a note to retry next week
<alyssa> KHR-GLES* seems like an excellent smoke test for "did I hose my driver"
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<alyssa> Gave that idea a try for Valhall
<alyssa> Unfortunately backfired because now the CVT unit is overloaded, ah well...
<alyssa> maybe Valhall needs a scheduler to balance the pipes after all. grumble.
<Venemo> alyssa: overloaded? whoah.
<alyssa> Venemo: CVT handles all the random instructions
<Venemo> aha
<alyssa> Everything but FMA, FADD, bitwise, and special functions.
<alyssa> In practice things seem to be FMA pipe bound, of course.
<alyssa> (Of the ALU bound set. In actual practice things are memory bandwidth bound :-p)
<alyssa> Venemo: Re your phi-undef MR, I do wonder if the extra reg pressure from keeping the condition live is a problem
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<Venemo> not a problem for us according to the stats, but who knows.
<alyssa> nod
<alyssa> Intriguing that patch is actually a win on Bifrost.
<alyssa> I guess because the clause scheduler can revert the opt when it hurts.
<Venemo> I also saw some strange behavior on intel, there may be a bug
<Venemo> same for aco actually
<alyssa> (I mean just the linked bifrost patch, not with your code.)
<Venemo> right, sorry
<Venemo> in one of the shaders there is a big chunk of CF deleted and I'm not quite sure why
<alyssa> oops
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<JPEW> Is there anyway to test my application that uses DMABUfs for offscreen rendering (/dev/dri/renderD128, think weston-simple-dmabuf-egl) on QEMU with software rendering? Nothing seems to be working out for me
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<gawin> thanks
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