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<alyssa> apparently I'm on FMA duty again
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<idr> Oh the joys of having to "see through" fneg and fabs. :(
<alyssa> idr: jekstrand told me you spent a lot of time on this for Intel, maybe we should just move the intel ffma pass back to core and add flags for the funny intel bits (2 constant cases maybe?)
<alyssa> though maybe that was flrp, not ffma
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<karolherbst> alyssa: oh wow... wondering why we don't catch that already
<alyssa> shrug
<alyssa> MR up
<alyssa> testing wanted
<idr> alyssa: I spent a lot of time on ffma and flrp... I won't say that I got a lot for that time, though.
<alyssa> idr: woof :-(
<idr> I have several branches where I was trying to improve the various ffma heuristics. Everything helped a bunch of shaders by a lot... and hurt a bunch of other shaders by a lot. :(
<alyssa> "got a lot" in terms of shaderdb or actual app fps?
<idr> Either.
<idr> When shader-db was basically a wash, I didn't even bother running apps.
<idr> With some of the other work that you and anholt have done, it might be worth revisiting some of that.
<idr> And... it might be different on drivers that... eh... have better schedulers.
<alyssa> I still want to review noltis
<alyssa> just do not have the brainpower right now
<alyssa> idr: speaking of fun heuristics
<anholt> alyssa: there was something funny with the total cost rolling over in a long test. I am suspicious of that part of the code.
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<anholt> but, also, need to just look at some regressed tests and add unit tests.
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<MrCooper> dv_: looks plausible, though HW might impose additional alignment constraints
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<karolherbst> why is hw...
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<CounterPillow> Verilog was created by Prabhu Goel, Phil Moorby, Chi-Lai Huang, and Douglas Warmke between late 1983 and early 1984.[3]
<CounterPillow> This has widely been regarded as "a mistake".
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<alyssa> anholt: +1
<alyssa> CounterPillow: that trakcs
<alyssa> tracks
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<kchibisov> What is the preferred extension for _sync_control with GLX? The EXT one or MESA?
<kchibisov> s/sync/swap/
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<tonyk> what's the name of IGT IRC channel?
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<karolherbst> jenatali: do you rely on readonly and writeonly images to have a split driver_location index?
<karolherbst> uhm.. actually forget about that, we need it split
<jenatali> What do you mean by split?
<jenatali> IIRC we make them both 0-indexed
<karolherbst> yeah...
<karolherbst> it has to be like that, I simply forgot why while cleaning up my texture code
<jenatali> Yeah, readonly are textures and writeonly (or readwrite) are images
<karolherbst> I was thinking about having one index for order/format intrinsics, but that obviously wouldn't work :)
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<karolherbst> I have to say.. I really like to use texture vars here. Makes some code more obvious about what's going on
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<deathmist> any way I could help with solving https://gitlab.freedesktop.org/mesa/mesa/-/issues/7555 (freedreno: X11/XWayland on Adreno 540 freezes updating screen entirely)? robclark or tarceri perhaps? I've locally reverted 34e868d882c (freedreno/ir3: tidy up duplication of common nir options)
<deathmist> wrong commit (I had another issue open), I meant 8192772c0ac (freedreno: Remap high/norm/low priorities)
<robclark> deathmist: maybe track down what submitqueue priorities it used before/after? Is something keeping the GPU continuously busy causing starvation?
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<deathmist> robclark: looking at https://gitlab.freedesktop.org/mesa/mesa/-/commit/8192772c0ac the priorities were hardcoded before, guess I'll add logging to check prio_low and prio_norm values it sets in fd_screen_create(); how would one check if something is "keeping the GPU continuously busy causing starvation"? I'd guess it's busy when it launches a new XWayland window under GNOME for
<deathmist> example
<deathmist> in my case I was testing Minecraft and simply trying to launch the game caused the display to stop refreshing before the window even becomes visible
<deathmist> entering an X11 session of GNOME also causes a similar effect where the display stops refreshing before a frame of the desktop environment is rendered
<robclark> what could be happening (and you should be checking for) is whether game ends up with higher priority (lower numerically) than the compositor (which I guess with x11 you need to care about both Xorg and gnome-shell processes)
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<idr> alyssa: RE #7539... Intel GPUs have a 3-source compare-and-select that matches NIR pretty closely, but we also have issues generating those instructions for all the same reasons we have issues with ffma.
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<alyssa> idr: Yeah, makes sense
<alyssa> You think 3-src is bad, try 4-src...
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<karolherbst> is there a IRC channel for v3d or something?
<alyssa> yes
<alyssa> but I do not remember the name (:
<alyssa> semeingly #videocore
<karolherbst> πŸ™ƒ
<karolherbst> ahh
<karolherbst> good enough
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<alyssa> zmike: can i introduce u to something cool
<alyssa> it's called gl_shader_stage_is_compute
<alyssa> very cool
<alyssa> "this was for supporting clover, but I don't care anymore" extremely-acked-by: alyssa rosenzweig <alyssa@collabora.com>
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<zmike> the rare eab
<jenatali> zmike: Yeah... that image typing stuff is the same problem I ran into :(
<jenatali> That test case I sent is the reason we potentially split the image into multiple vars if it's used that way
<zmike> I might do that too, but probably not something I'm concerned with during initial bringup since it passes CTS like this
<karolherbst> I am sure we'll have to do more fixes once we want to have valid spir-v
<karolherbst> but from a quick look that MR already looks much better than the code you came up before
<zmike> I helps that you're not feeding me complete trash anymore :p
<karolherbst> :D
<karolherbst> though I really have to fix the DCE stuff, because normally if sampler/texture derefs are lowered the shader can consider the variables to be dead :/
<karolherbst> but it should also like not matter at all for images
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<alyssa> jenatali: okay potentially dumb question
<alyssa> I hear that dx12 and zink can't lower I/O, they need nir_variable's
<alyssa> Why is that?
<alyssa> Why can't they lower I/O and then translate lowered I/O into indexing into a big array?
<alyssa> it's immaterial to my life, just curious
<airlied> do you still have array bounds info after io lowering?
<jenatali> alyssa: At least from the DXIL level, and I think SPIR-V is the same, the IR needs to upfront-declare what's going to be accessed, including which components will be int/uint/float, interpolation modes, system values, etc
<jenatali> You could reconstruct all of that from the lowered I/O... but all that info is in the variables already, since that's how GLSL is structured, so why delete it and reconstruct it when we can just.. not delete it?
<jenatali> It's simpler to iterate the variables first to generate those declarations, then iterate the IR independently
<jenatali> Array bounds is a good one too
<alyssa> jenatali: Oh, weird, okay
<alyssa> I guess that makes sense? I guess if I were generating GLSL i'd have the same problem
<alyssa> airlied: firm maybe(TM)
<alyssa> io_semantics claims to have something for it
<jenatali> alyssa: FWIW I switched us to lowered I/O a while ago instead of derefs, I just don't delete the vars afterwards
<jenatali> In DXIL at least, you declare the vars and give them indices upfront, and then you reference them by indices later on, so it's simpler to just use the lowered I/O vals rather than computing them in the backend from derefs
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<alyssa> sure
<alyssa> jenatali: basically my concern is wanting to be able to run passes like lower_fragcolor after lowering I/O
<alyssa> and that doesn't work when Zink uses them on non-lowered I/O
<jenatali> Ack, makes sense
<alyssa> without maintaining 2 code paths -.-
<jenatali> Yeah...
<jenatali> If it gets to the point that we're the only holdout on non-lowered I/O, I could probably reconstruct the I/O vars from the shader if I had to
<alyssa> eh, Zink needs what Zink needs
<alyssa> but it would be nice to do lower_fragcolor on lowered I/O
<alyssa> because otherwise I can't lower I/O in pipe->finalize_nir
<jenatali> And I'm thankful it exists to keep us from being the only one using non-lowered I/O :)
<alyssa> haha
<alyssa> fragcolor, texcoord_replace, clip_fs, viewport_transform, point_size
<alyssa> ...would all need to be adapted for lowered I/O for bifrost to switch anyway
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<karolherbst> yeah.. I wished we'd have better ways, but some drivers might really just want to use derefs :/
* alyssa doesn't really carwe
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<karolherbst> do we have a generic impl for clear_texture?
<karolherbst> I am always bad at finding those :/
<karolherbst> ohh duh.. panfrust uses it :/
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<jekstrand> Ugh... Meta for NVK isn't going to be as nice as I'd hoped. :-/
<karolherbst> why not?
<jekstrand> Depth/stencil
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<jekstrand> Also, I think NV can do MSAA resolves in a single sample operation if I set magic image view bits.
<karolherbst> probably
<jekstrand> The question is how to take advantage of all that
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* karolherbst builds the CL CTS on the pi4
<jekstrand> For depth/stencil, I need to bind as a color image and render to it.
<karolherbst> "fun"
<jekstrand> None of it's that hard. It's just hard to do in generic code
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<karolherbst> I think that was also the reason we couldn't use u_blitter
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<airlied> jekstrand: yeah generic resolve is messy, esp after looking at how much trouble it is on amd hw
<airlied> the whole fixed fn hw vs compute path vs fragment path is a lot of not fun
<jekstrand> Well, NV doesn't really need many paths. It just needs a bit of custom around depth/stencil
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<jekstrand> There's a bit of annoyance in dealing with blit regions but that by itself isn't worth common code
<jekstrand> Yeah, I think I'm gonna pull this into nvk and vendor it. :-/
<jekstrand> Makes me sad
<karolherbst> :(
<karolherbst> soo.. going to do my first CTS run soon, any bets?
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<alyssa> jekstrand: "this" being resolves?
<alyssa> or all of meta? o_O
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<karolherbst> uhhh.. that pi4 is so slow :(
<alyssa> karolherbst: now you know why panfrosticl isn't conformant :(
<karolherbst> I thought that's because of weirdo bugs :D
<karolherbst> give me the hardware and I'll run it :P
<karolherbst> though for a first try it's not even that terribly broken: "Pass 752 Fails 27 Crashes 806 Timeouts 0: 65%|"
<karolherbst> something is totally bonkers with compute shaders though
<karolherbst> alyssa: you were targeting EMBEDDED or FULL profile?
<alyssa> Embedded, though there's a weirdo bug where rusticl won't pass CTS without int64
<alyssa> so all full would add is more images/samplers
<alyssa> which panfrost can and probably should do?
<alyssa> Arm does the full profile
<karolherbst> full profile CTS runs like 16 times as long though
<karolherbst> but yeah... could be doable but maybe also very pointless
<karolherbst> could pass embedded first and upgrade later
<alyssa> Yikes!
<alyssa> yes, that was another reason to avoid full profile :(
<karolherbst> that's on iris: Test Conversions passed in 28495.6525979s
<alyssa> O_O
<karolherbst> second longest running test: Test Math passed in 10113.4281409s
<karolherbst> the it's like "Test Half Ops passed in 2179.17991304s" and it quickly goes down
<jenatali> karolherbst: That's 8 hours for conversions?
<jenatali> Not bad
<karolherbst> yeah
<karolherbst> the full run is like 13 hours as you see
<jenatali> Yeah that sounds about right
<jenatali> I tried to do a full run on WARP... took ~3 days IIRC
<karolherbst> there is one thing I wanted to try out: offloading callbacks
<jenatali> Offloading?
<karolherbst> atm I do that in the worker thread
<karolherbst> so instead of calling into the callbacks synced in the worker thread, I just push that out into a callback thread
<jenatali> I wouldn't expect that to make much of a difference
<karolherbst> not sure how badly that messes up API promises though
<karolherbst> ohh.. it's mostly for making sure the GPU has enough stuff to work through
<HdkR> karolherbst: This is why I only ever recommend pi if you enjoy pain. It's just /way/ too slow. They could at least give us the courtesy of a Pi5 with like ten A510 cores or something :P
<karolherbst> and it might or might not speed up the CTS
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<HdkR> If I read the CL spec correctly then the callbacks can happen on whatever thread, so if CTS breaks then CTS is broken :D
<karolherbst> right...
<jenatali> Yeah, callbacks can happen wherever
<karolherbst> but the rpi4 is at least at 100% load.. should have built mesa in release mode...
<HdkR> Which is why I funnel them through a tube, so I can control the damn things
<jenatali> I think I'm almost done with this CL interop extension
<karolherbst> HdkR: when is it ready tho
<karolherbst> ohh, saw your message oops
<HdkR> hah
<karolherbst> though my rpi4 doesn't display anything once the GPU driver loads...
<alyssa> HdkR: this is why I recommend tau instead
<alyssa> much less pain
<karolherbst> the CTS turned around, yay "Pass 877 Fails 35 Crashes 838 Timeouts 0: 71%|"
<karolherbst> more passes than fails
<karolherbst> but why do compute shaders not work :( ... ohhhh
<karolherbst> duh
<karolherbst> because they are kernels
<karolherbst> MESA_SHADER_KERNEL was a mistake
<alyssa> karolherbst: agreed, kill it with fire
<alyssa> sequel to the drawoverhead MR
<karolherbst> some drivers want to know it though :(
<karolherbst> like zink
<alyssa> then those drivers are wrong ~~and should be deleted~~
* karolherbst grabs 🍿🍿🍿
<alyssa> at the very least make "is opencl?" a shader_info bit?
<alyssa> instead of a duplicate shader stage
<karolherbst> mhhhh
<karolherbst> that might be a good compromise indeed
<alyssa> I can't even tell what parts of the tree actually care because there's so much "compute || kernel" duplicatio
<karolherbst> yeah....
<karolherbst> though I think earlier the goal wasn't to make them as close as possible, because of $reasons
<HdkR> Obviously since kernels would be written in SPIR
<karolherbst> obviously
<HdkR> If I had to accept SPIR I would have also tried removing from the codebase as much as possible as well :D
<karolherbst> "Pass 1273 Fails 42 Crashes 1134 Timeouts 0: 100%"
<karolherbst> well.. that's surprising
<karolherbst> given the hardware probably had never seen CL in its entire life
<alyssa> eyyy
<karolherbst> let me fix running kernels and do another run
<karolherbst> :D
<jenatali> HdkR: SPIR's not too hard to accept as long as you have a copy of LLVM linked in
<HdkR> But then you have a version locked copy of LLVM linked in.
<karolherbst> I also think that shader caching is somewhat busted...
<jenatali> No, doesn't need to be version locked, LLVM's bitcode reader is backwards compatible
<HdkR> LLVM doesn't guarantee backwards compatibility though?
<jenatali> Not for the writer, but the reader they do try
<jenatali> For things like SPIR
<karolherbst> alyssa: what was that name of that handy is compute/kernel function?
<HdkR> huh, TIL
<karolherbst> ohh wait.. I know a weirdo trick
<HdkR> Wonder how often that breaks, because it sounds like constantly.
<jenatali> Yeah, dunno
<jekstrand> alyssa: both, a bit?
<jekstrand> alyssa: I'm starting to get an idea how I can handle it, though.
<karolherbst> huh...
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<jekstrand> alyssa: Basically, a pair of functions, one of which translates the API format to the "real" format you want to use and another which takes the API format, color, depth, and stencil components and packs them all into a color thing however the driver wants.
<jekstrand> IDK if that's general enough, though.
<karolherbst> why can't v3d deal with 64 bit uniforms :(
<alyssa> jekstrand: Hm. I was really looking forward to vk_meta, idk
<jekstrand> alyssa: I think it's probably still possible
<alyssa> Meta is the most frustrating part of panvk to me, whereas there's 0 meta stuff in our gl driver because u_blitter can do everything we care about.
<jekstrand> Sure
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<jekstrand> Hrm... Another option would be to make the driver handle all that stuff in vkCreateGraphicsPipeline if it sees a depth/stencil format bound as a color attachment.
<jekstrand> That could work, too.
<jekstrand> That actually doesn't sound insane...
<jekstrand> At least, no more insane than anything else I'd do. :joy:
<alyssa> :grin:
<alyssa> :ship-it-parrot:
<jekstrand> Hrm... But how would that work. :-/
<alyssa> jekstrand: What does colour rendering to Z/S even mean? I'm lost.
<alyssa> What's prompting this?
<jekstrand> alyssa: blits and resolves of Z/S
<jekstrand> Depth you can do by just setting gl_FragDepth. Stencil requires magic.
<jekstrand> Either EXT_shader_stencil_export (which NV doesn't have) or you have to bind stencil as a regular old render attachment
<alyssa> All of my hardware has EXT_shader_stencil_export so I've avoided that one thus far.
<jekstrand> That makes everything easier. :)
<alyssa> What's wrong with binding the stencil image as R8_UINT?
<alyssa> Compression/tiling fun?
<jekstrand> Well, for one thing, "stencil image" isn't a thing... NVIDIA does interleaved depth/stencil. :sweat_smile:
<alyssa> ...Delight.
<karolherbst> it makes perfect sense :P
<alyssa> Yes, I see why blits of Z24S8 are problematic.
<alyssa> Apple solves that by not support Z24 or interleaved (-:
<jekstrand> Very sensible. :P
<alyssa> :-D
<jekstrand> In any case, it's all very implementable. It just takes a bit of work.
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<alyssa> I still haven't manage to convince myself whether emulating Z24 as Z32F is conformant or not.
<alyssa> Z24 does have better precision near 1 than Z32F
<jekstrand> And it takes some thought to figure out exactly how to architect all the driver knobs to make it work.
<alyssa> But can you ever observe that extra precision?
<alyssa> If a few ulps fall in a forest and nobody's instruments are fine enough to observe them, is that conformant?
<karolherbst> ohh.. figured out why v3d breaks.. it's full 32 bit.. delight
<alyssa> :-p
<alyssa> (...But what if we throw fp64 emulation in the arena?)
<airlied> alyssa: just don't expose Z24 for vulkan :-)
<karolherbst> "Unknown intrinsic: vec1 32 con ssa_1 = intrinsic load_kernel_input (ssa_0) (base=0, range=0, align_mul=256, align_offset=0)"
<karolherbst> how rude
<alyssa> airlied: :-D
<alyssa> u_transfer_helper stuff seems to work ... I think
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<alyssa> karolherbst: So there's this great Rusticl merge request someone did that makes load_kernel_input go away entirely, consider giving it a try? :-p
<karolherbst> only if you lower uniforms to ubos
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<karolherbst> or what did you mean?
<karolherbst> ohh on v3d
<karolherbst> nah.. they don't lower uniforms :(
<karolherbst> well
<karolherbst> they lower it themselves, _but_ they lower it to be per byte, so this is nice, because I can just short circuit it then
<karolherbst> "intr->intrinsic = nir_intrinsic_load_uniform;" done
<karolherbst> "Unknown intrinsic: vec3 32 con ssa_6 = intrinsic load_workgroup_size () ()" mhhh
<karolherbst> that's weird..
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<karolherbst> ahh, it has index
<karolherbst> okay.. how did that work again
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<karolherbst> .....
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<karolherbst> it ooms... nice
<karolherbst> ehh "Max memory allocation 2147483648 (2GiB)" yeah.. please don't
<alyssa> Whoops
<karolherbst> well.. that's actually fine, but huh...
<karolherbst> it still ooms for reasons I don't get
<karolherbst> maybe some leak somewhere...
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<karolherbst> ohh it loops forever in lower_compute_system_value_instr
<karolherbst> whelp "vec3 32 ssa_6472182 = intrinsic load_workgroup_size () ()"
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<karolherbst> "Unknown intrinsic: vec1 32 div ssa_75 = intrinsic load_global (ssa_74) (access=0, align_mul=4, align_offset=0)" figures...
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<zmike> did v3dv not work out of the box?
<karolherbst> nope
<karolherbst> ohh wait.. v3dv..
<karolherbst> no, I test v3d atm